Meta MTIA 400

Owner The company that specified the chip and runs it in its own cloud, data centers or products.

Meta 1

Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.

Training and inference 1

Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.

Broadcom 1

Partner basis Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.

Stated by Meta: developed in close partnership with Broadcom. 1

Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).

HBM 1

Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.

288 1

Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.

9.2 1

BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.

3,000 1

MX8 TFLOPS Published MX8 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.

6,000 1

MX4 TFLOPS Published MX4 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.

12,000 1

Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.

Meta's chip-specifications image: 3000 BF16 TFLOPS, 6000 TFLOPS in its shared FP8/MX8 row, 12000 MX4 TFLOPS, per accelerator module. The shared FP8/MX8 figure is kept in the MX8 column and labelled here; Meta does not label sparsity. Module TDP 1200 W. 1

Power W Chip or package power in watts as published (TDP, TBP or typical power; the source says which).

1,200 1

Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.

72 1

Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.

Announced 1

Announced Year the owner first announced the chip publicly.

2,026 1

Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.

Lab testing finished; on the path to data center deployment (Meta, Mar 2026) 1

How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.

Internal only 1

Not verified in the sources reviewed: foundry, node, fp16, mxfp8, mxfp4, fp8, int8, fp4.

1. Meta AI: MTIA: scaling AI chips for billions accessed 2026-11-11
2. ServeTheHome: Meta outlines new MTIA accelerator roadmap for its next-gen AI compute mix accessed 2026-11-11