# Custom Silicon List > 42 custom chips from 9 owners, 24 of them deployed. Microsoft Maia 200 leads stated FP8 at over 5,000 TFLOPS per chip, Google TPU 8i has the largest fixed HBM entry at 288 GB, and Broadcom is the named partner on 11. Every figure keeps its precision and links its source. Every custom AI chip, down to the precision of each FLOP. 42 chips, each field linked to its public source, last verified 2026-11-11. When citing, link the canonical HTML page. ## Data - [Custom AI chips, compared](https://customsiliconlist.com/): the full comparison table - [Data (JSON)](https://customsiliconlist.com/data.json): every record with sources - [Data (CSV)](https://customsiliconlist.com/data.csv): one row per chip - [Methodology](https://customsiliconlist.com/methodology/): what each field means and how it is verified ## Chips - [Alibaba T-Head Zhenwu 810E](https://customsiliconlist.com/alibaba-zhenwu-810e/): Alibaba's in-house AI accelerator (the T-Head PPU): 96 GB of HBM2e at 2.77 TB/s, 700 GB/s chip-to-chip links and 400 W, running in 10,000-card clusters on Alibaba Cloud for more than 400 customers. - [Alibaba T-Head Zhenwu M890](https://customsiliconlist.com/alibaba-zhenwu-m890/): T-Head's 2026 accelerator: 144 GB of HBM, 800 GB/s chip-to-chip links and three times the 810E's performance, shown at Alibaba Cloud Summit with a 128-chip supernode server. The V900 follows in 3Q27. - [AWS Graviton4](https://customsiliconlist.com/aws-graviton4/): Amazon's fourth Arm server CPU: 96 cores per socket and DDR5-5600 memory, generally available in EC2 R8g instances since July 2024 and paired with Trainium in AWS AI racks. - [AWS Graviton5](https://customsiliconlist.com/aws-graviton5/): Amazon's fifth Arm server CPU: 192 Neoverse V3 cores on TSMC 3 nm in one socket, a 5x larger L3 cache than Graviton4 and DDR5-8800 memory, generally available in EC2 M9g, C9g and R9g instances in 2026. - [AWS Inferentia](https://customsiliconlist.com/aws-inferentia/): Amazon's first in-house machine learning chip, announced at re:Invent 2018: four NeuronCores, 128 INT8 TOPS and 8 GB of on-board DRAM, sold through EC2 Inf1 instances with up to 16 chips. - [AWS Inferentia2](https://customsiliconlist.com/aws-inferentia2/): Amazon's second inference chip: 32 GB of HBM, 190 FP16/BF16 TFLOPS and 380 INT8 TOPS per chip, rented through EC2 Inf2 instances. - [AWS Trainium](https://customsiliconlist.com/aws-trainium/): Amazon's first training chip: 32 GB of HBM and 190 BF16 TFLOPS per chip, with 16 chips in each EC2 Trn1 instance. - [AWS Trainium2](https://customsiliconlist.com/aws-trainium2/): The chip behind Project Rainier: 96 GiB of HBM, 1,299 FP8 TFLOPS per chip, 64 chips per Trn2 UltraServer and nearly 500,000 chips in the Rainier cluster that Anthropic uses to build and deploy Claude. - [AWS Trainium3](https://customsiliconlist.com/aws-trainium3/): Amazon's first 3 nm AI chip: 144 GB of HBM3E at 4.9 TB/s and 2,517 MXFP8 TFLOPS per chip, with 144 chips per Trn3 UltraServer. Generally available since December 2025, with customers including Anthropic. - [AWS Trainium4](https://customsiliconlist.com/aws-trainium4/): AWS announced Trainium4 alongside Trainium3 in December 2025. Its roadmap targets at least six times Trainium3’s FP4 compute and four times its memory bandwidth, with delivery expected in 2027. - [Baidu Kunlunxin M100](https://customsiliconlist.com/baidu-kunlun-m100/): Baidu unveiled Kunlun M100 at Baidu World in November 2025 for large-scale inference, including mixture-of-experts models. The announced launch target is early 2026; a target date alone is not evidence of deployment. - [Baidu Kunlunxin M300](https://customsiliconlist.com/baidu-kunlun-m300/): Baidu unveiled Kunlun M300 at Baidu World in November 2025 for training and inference of large multimodal models. The announced launch target is early 2027; a target date alone is not evidence of deployment. - [Baidu Kunlunxin P800](https://customsiliconlist.com/baidu-kunlun-p800/): Baidu's third-generation Kunlun chip: 96 GB of HBM and 345 FP16 TFLOPS. Baidu powered up a 30,000-chip P800 cluster in April 2025 to train DeepSeek-class models, and it packs 256 of them into one Tianchi supernode. - [Google Axion](https://customsiliconlist.com/google-axion/): Axion is Google's first custom Arm data center CPU, built on Neoverse V2, with up to 50% better performance and 60% better energy efficiency than comparable x86 instances. It runs Google services such as Bigtable, Spanner, BigQuery and YouTube Ads. - [Google TPU 8i](https://customsiliconlist.com/google-tpu-8i/): TPU 8i is Google's eighth-generation inference chip for sampling, serving and reasoning, with 288 GB of HBM at 8.6 TB/s and 384 MB of on-chip SRAM. Google rates it at up to 80% better inference price-performance than Ironwood. - [Google TPU 8t](https://customsiliconlist.com/google-tpu-8t/): TPU 8t is Google's eighth-generation training chip, with 12.6 PFLOPS FP4 and 216 GB of HBM per chip, 9,600 chips per superpod and over 134,000 chips on one Virgo fabric. Google rates it at up to 2.7x the training price-performance of Ironwood. - [Google TPU v4](https://customsiliconlist.com/google-tpu-v4/): Google's fourth-generation TPU links 4,096 chips per pod through optical circuit switches for more than one exaflop of BF16 compute. Each chip delivers 275 TFLOPS BF16/INT8 with 32 GiB of HBM2. - [Google TPU v5e](https://customsiliconlist.com/google-tpu-v5e/): Google's cost-optimized TPU for training and serving, with 197 TFLOPS BF16 and 393 TOPS INT8 per chip in 256-chip pods. Google rates it at up to 2.5x the inference performance per dollar of TPU v4. - [Google TPU v5p](https://customsiliconlist.com/google-tpu-v5p/): Google's performance TPU, launched in December 2023 with 8,960 chips per pod and 459 TFLOPS BF16 per chip. Google says it trains large LLMs 2.8x faster per chip than TPU v4. - [Google TPU v6e Trillium](https://customsiliconlist.com/google-tpu-v6e-trillium/): Trillium, Google's sixth-generation TPU, delivers 918 TFLOPS BF16 per chip, a 4.7x jump in peak compute, and trained Gemini 2.0. Google scales it past 100,000 chips on one Jupiter network fabric. - [Google TPU v7 Ironwood](https://customsiliconlist.com/google-tpu-v7-ironwood/): Ironwood, Google's seventh-generation TPU, packs 4,614 TFLOPS FP8 and 192 GB of HBM per chip and scales to 9,216 liquid-cooled chips in one superpod. Anthropic plans to access up to 1 million TPUs, and Broadcom's CEO said Broadcom took a $10 billion order to sell Ironwood racks to Anthropic. - [Huawei Ascend 910B](https://customsiliconlist.com/huawei-ascend-910b/): Huawei's workhorse AI chip in China since 2023: 64 GB of HBM2e at 1.6 TB/s on SMIC's 7 nm (N+2) process, rented through Huawei Cloud and bought by Baidu, Tencent and iFLYTEK. - [Huawei Ascend 910C](https://customsiliconlist.com/huawei-ascend-910c/): Two compute dies in one package: 752 dense FP16/BF16 TFLOPS, 128 GB of HBM at 3.2 TB/s, and 384 chips per CloudMatrix 384 supernode. Huawei has deployed more than 300 Atlas 900 A3 SuperPoDs. - [Huawei Ascend 950DT](https://customsiliconlist.com/huawei-ascend-950dt/): The training and decode variant of the Ascend 950: 144 GB of Huawei's HiZQ 2.0 HBM at 4 TB/s, 1 PFLOPS FP8, and up to 8,192 chips in one Atlas 950 SuperPoD. The SuperPoD is in testing, with volume supply from the end of 2026. - [Huawei Ascend 950PR](https://customsiliconlist.com/huawei-ascend-950pr/): Huawei's inference and recommendation chip on the new Ascend 950 die: 1 PFLOPS FP8 and 2 PFLOPS MXFP4, with Huawei's own low-cost HiBL 1.0 HBM. Shipping in limited volumes in 2026, and Huawei says it sells every unit it can make. - [Huawei Ascend 960](https://customsiliconlist.com/huawei-ascend-960/): Huawei's 2027 chip: 2 PFLOPS FP8 and 4 PFLOPS FP4, double the Ascend 950's compute, memory capacity and bandwidth, and up to 15,488 chips in one Atlas 960 SuperPoD. Due in the fourth quarter of 2027. - [Huawei Ascend 970](https://customsiliconlist.com/huawei-ascend-970/): Huawei’s announced Ascend 970 roadmap targets training and inference, with market availability planned for the fourth quarter of 2028. Its original roadmap describes relative performance targets rather than final specifications. - [Meta MTIA 300](https://customsiliconlist.com/meta-mtia-300/): MTIA 300 is the base of Meta's chiplet roadmap, developed in close partnership with Broadcom and in production for ranking and recommendation training. Meta has deployed hundreds of thousands of MTIA chips in production. - [Meta MTIA 400](https://customsiliconlist.com/meta-mtia-400/): MTIA 400 is Meta's Broadcom-partnered inference chip with 9.2 TB/s of HBM bandwidth and 400% more FP8 compute than MTIA 300. Seventy-two MTIA 400s form one switched scale-up rack. - [Meta MTIA 450](https://customsiliconlist.com/meta-mtia-450/): MTIA 450 doubles MTIA 400's HBM bandwidth to 18.4 TB/s and lifts MX4 compute 75% for generative AI inference. Meta schedules it for mass deployment in early 2027. - [Meta MTIA 500](https://customsiliconlist.com/meta-mtia-500/): MTIA 500 is Meta's 2x2-chiplet inference flagship with 27.6 TB/s of HBM bandwidth, 4.5x MTIA 300, and up to 80% more HBM capacity than MTIA 450. Meta schedules it for mass deployment in 2027. - [Meta MTIA v1](https://customsiliconlist.com/meta-mtia-v1/): Meta's first in-house AI accelerator, built for its recommendation workloads on TSMC 7nm, delivers 102.4 TOPS INT8 at just 25 W. Meta now calls it MTIA 100. - [Meta MTIA v2](https://customsiliconlist.com/meta-mtia-v2/): Meta's second-generation MTIA: 354 TOPS INT8 on TSMC 5nm at 90 W, up to 72 accelerators per rack and 3x the performance of MTIA v1 across four Meta models. Meta went from first silicon to production models in 16 regions in under nine months. - [Microsoft Cobalt 100](https://customsiliconlist.com/microsoft-cobalt-100/): Cobalt 100 is Microsoft's first in-house Arm server CPU, a 128-core chip powering Microsoft Teams and Azure SQL. Azure Cobalt 100 VMs launched in 14 regions with up to 1.4x the CPU performance of earlier Azure Arm VMs. - [Microsoft Cobalt 200](https://customsiliconlist.com/microsoft-cobalt-200/): Cobalt 200 is Microsoft's second Arm server CPU: 132 Neoverse V3 cores across two chiplets on TSMC 3nm, with up to 50% better CPU performance than Cobalt 100. Azure Cobalt 200 VMs are in early access preview in eight regions. - [Microsoft Maia 100](https://customsiliconlist.com/microsoft-maia-100/): Maia 100 is Microsoft's first custom AI accelerator: 105 billion transistors on TSMC 5nm with 64 GB of HBM2E, built for AI workloads on Azure. Microsoft runs it at 500 W per accelerator for inference. - [Microsoft Maia 200](https://customsiliconlist.com/microsoft-maia-200/): Maia 200 is Microsoft's inference accelerator on TSMC 3nm, with a stated minimum of 10 PFLOPS FP4 and 5 PFLOPS FP8, plus 216 GB of HBM3E at 7 TB/s. It serves OpenAI's GPT-5.2 models and Microsoft 365 Copilot and is rolling out across Azure in the US, Europe and Australia. - [Microsoft Maia 300](https://customsiliconlist.com/microsoft-maia-300/): Maia 300 is Microsoft's next inference accelerator, with compute chiplets on TSMC N2P and eight HBM4 stacks delivering 18 TB/s at 950 W. Microsoft puts 96 in each rack and starts production deployments in 2027. - [OpenAI Jalapeño](https://customsiliconlist.com/openai-jalapeno/): OpenAI's first custom chip, an LLM inference processor co-developed with Broadcom from first design to tape-out in nine months. Engineering samples run GPT-5.3-Codex-Spark at target frequency and power, with first deployment set for the end of 2026. - [Tesla AI5](https://customsiliconlist.com/tesla-ai5/): Tesla's fifth-generation in-house AI chip for its cars and Optimus robots, taped out in April 2026. Musk puts it at up to 10x AI4; TSMC and Samsung both build it, with volume production in 2027. - [Tesla AI6](https://customsiliconlist.com/tesla-ai6/): Tesla's next in-house AI chip, to be made entirely by Samsung under a $16.5 billion foundry contract running to 2033 at Samsung's Taylor, Texas fab. - [Tesla Dojo D1](https://customsiliconlist.com/tesla-dojo-d1/): Tesla's in-house training chip for the Dojo supercomputer: 50 billion transistors on a 645 mm² die, made by TSMC at 7 nm, in production from July 2023. Tesla shut Dojo down in August 2025 to focus on AI6. ## Optional - [All records in one file](https://customsiliconlist.com/llms-full.txt) - [Sitemap](https://customsiliconlist.com/sitemap.xml)