Google TPU 8i
TPU 8i is Google's eighth-generation inference chip for sampling, serving and reasoning, with 288 GB of HBM at 8.6 TB/s and 384 MB of on-chip SRAM. Google rates it at up to 80% better inference price-performance than Ironwood. Sources and verification dates.
Every published figure
Source per value- Owner The company that specified the chip and runs it in its own cloud, data centers or products.
- Google 1
- Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
- Inference 1
- Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.
- Broadcom 3
- Partner basis Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.
- Stated by Broadcom CEO Hock Tan on Broadcom's Q3 FY2026 earnings call (Motley Fool transcript): Broadcom ships TPU 8i, MediaTek builds TPU 8t. Google has not confirmed. 3
- Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
- 288 1
- Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.
- 8.601 1
- FP4 TFLOPS Published FP4 throughput per chip or accelerator module in TFLOPS. MXFP4 and MX4 have separate columns; see the precision note for scope.
- 10,100 1
- Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
- Google states 10.1 PFLOPS peak FP4 per chip; no FP8 or BF16 figure published. 384 MB on-chip SRAM, Boardfly topology, Arm Axion host. Up to 1,152 chips connected (1,024 active per pod). TPU 8i Max (Nov 2026) puts two 8i chips on one package. 1
- Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
- 1,152 1
- Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
- Announced 1
- Announced Year the owner first announced the chip publicly.
- 2,026 1
Not verified in the sources reviewed: foundry, node, memory, bf16, fp16, mxfp8, mxfp4, mx8, mx4, fp8, int8, power, deployment scale, how to get it.
Sources
- Google Cloud Blog: TPU 8t and TPU 8i technical deep dive accessed 2026-11-11
- Google: Our newest TPUs: 8tx and 8i Max, built for the agentic era accessed 2026-11-11
- Broadcom Q3 FY2026 earnings call: Hock Tan names Broadcom TPU 8i and MediaTek v8t accessed 2026-11-11