Alibaba T-Head Zhenwu M890

Owner The company that specified the chip and runs it in its own cloud, data centers or products.

Alibaba 1

Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.

Training and inference 1

Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.

In-house (T-Head) 1

Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).

HBM 1

Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.

144 1

Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.

No FLOPS figure published; T-Head states three times the Zhenwu 810E's performance. 1

Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.

128 1

Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.

Announced 1

Announced Year the owner first announced the chip publicly.

2,026 1

Not verified in the sources reviewed: partner basis, foundry, node, memory bandwidth, bf16, fp16, mxfp8, mxfp4, mx8, mx4, fp8, int8, fp4, power, deployment scale, how to get it.

1. TrendForce: Alibaba T-Head unveils Zhenwu M890 with 3x performance accessed 2026-11-11