Methodology
42 chips, 79 sources, one precision per FLOPS column, a date on every row. Last full check 11 Nov 2026.
What counts as custom silicon
A chip is in scope when the company that runs it specified it for its own cloud, data centers or products: Google TPU, AWS Trainium and Inferentia, Meta MTIA, Microsoft Maia, OpenAI Jalapeño, Tesla Dojo and AI5. Chinese platform owners are in on the same rule: Huawei runs Ascend in Huawei Cloud, Alibaba runs Zhenwu in Alibaba Cloud and Baidu runs Kunlun in Baidu AI Cloud, even where they also sell the chip to others. The hyperscalers’ own Arm server CPUs (Graviton, Axion, Cobalt) sit in their own list because they host the accelerators.
Merchant chip vendors whose business is selling accelerators to everyone, such as NVIDIA, AMD, Intel Gaudi, Cerebras and Groq, are out of scope.
One record per generation
Each chip generation is its own row: TPU v5e and v5p are two records, Trainium2 and Trainium3 are two records. A variant that shares silicon with another chip goes in that chip’s precision note. A record goes live only with at least three sourced fields beyond name, URL and summary.
Where the data comes from
In this order: the owner’s announcement, product page, docs or earnings call; the design partner’s or foundry’s statement; technical papers and conference talks; then named trade press with original reporting (Reuters, The Register, TrendForce, ServeTheHome, Data Center Dynamics, TechCrunch, CNBC and similar). Every field lists the source that states it and the date we read it.
FLOPS stay tied to their precision
Each throughput column names one format: BF16, FP16, FP8, FP4, MXFP8, MXFP4, MX8 or MX4; INT8 uses TOPS. Chip and accelerator-module scope, shared-format rows, sparsity and ranges stay in the precision note. Relative roadmap targets stay in notes; we never multiply them into an absolute throughput figure. Meta’s chip-specifications image is a source alongside its article text.
Design partners
A partner is listed when the owner, the partner, a filing or named trade press says so. In-house means the owner says its own team designed the chip; the team (Annapurna Labs, HiSilicon, T-Head, Kunlunxin) is named in brackets.
Status and dates
Preview means early customer access, without a general availability claim. A roadmap date passing does not prove deployment. Announced year means the owner’s public announcement, not mass production or the date a rumor appeared. A blank means the announcement date was not verified.
Corrections
Owners, partners and readers can send corrections to hello@customsiliconlist.com with a public source. We update the row and its verified date. Featured placement is paid and labelled; it never changes a row’s data or its position in the sorted table.
Reuse
The dataset is free to reuse under CC BY 4.0 with a link to customsiliconlist.com. Download it as CSV or JSON.
Field definitions
26 fields- Owner
- The company that specified the chip and runs it in its own cloud, data centers or products.
- Role
- What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
- Design partner
- The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.
- Partner basis
- Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.
- Foundry
- The fab that manufactures the die (TSMC, Samsung, SMIC, Intel).
- Node
- Process node as the owner or foundry states it, for example 'TSMC N3' or '7 nm'.
- Memory
- On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).
- Memory capacity GB
- On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
- Memory bandwidth TB/s
- Peak memory bandwidth per chip in TB/s, as published.
- BF16 TFLOPS
- Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.
- FP16 TFLOPS
- Published FP16 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.
- MXFP8 TFLOPS
- Published MXFP8 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.
- MXFP4 TFLOPS
- Published MXFP4 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.
- MX8 TFLOPS
- Published MX8 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.
- MX4 TFLOPS
- Published MX4 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.
- FP8 TFLOPS
- Published peak FP8 throughput per chip in TFLOPS. The precision note records sparsity where the owner states it. Blank when the owner gives no FP8 figure.
- INT8 TOPS
- Peak INT8 throughput per chip in TOPS, as published. Mostly given for inference chips.
- FP4 TFLOPS
- Published FP4 throughput per chip or accelerator module in TFLOPS. MXFP4 and MX4 have separate columns; see the precision note for scope.
- Precision note
- What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
- CPU cores
- Cores per socket, for server CPUs.
- Power W
- Chip or package power in watts as published (TDP, TBP or typical power; the source says which).
- Largest pod chips
- The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
- Status
- Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
- Announced
- Year the owner first announced the chip publicly.
- Deployment scale
- The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.
- How to get it
- How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.