{ "name": "Custom AI chips, compared", "url": "https://customsiliconlist.com/", "license": "CC BY 4.0", "cite": "Custom Silicon List, https://customsiliconlist.com/", "updated": "2026-11-11", "fields": [ { "key": "owner", "label": "Owner", "type": "string", "description": "The company that specified the chip and runs it in its own cloud, data centers or products.", "filterable": false, "sortable": true }, { "key": "role", "label": "Role", "type": "enum", "description": "What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.", "filterable": true, "sortable": true, "enumValues": [ "Training and inference", "Inference", "Training", "Server CPU" ] }, { "key": "design_partner", "label": "Design partner", "type": "string", "description": "The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.", "filterable": false, "sortable": true }, { "key": "partner_basis", "label": "Partner basis", "type": "string", "description": "Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.", "filterable": false, "sortable": false }, { "key": "foundry", "label": "Foundry", "type": "string", "description": "The fab that manufactures the die (TSMC, Samsung, SMIC, Intel).", "filterable": false, "sortable": true }, { "key": "process_node", "label": "Node", "type": "string", "description": "Process node as the owner or foundry states it, for example 'TSMC N3' or '7 nm'.", "filterable": false, "sortable": true }, { "key": "hbm_type", "label": "Memory", "type": "string", "description": "On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).", "filterable": false, "sortable": true }, { "key": "hbm_gb", "label": "Memory capacity", "type": "number", "unit": "GB", "description": "On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.", "filterable": true, "sortable": true }, { "key": "mem_bw_tbs", "label": "Memory bandwidth", "type": "number", "unit": "TB/s", "description": "Peak memory bandwidth per chip in TB/s, as published.", "filterable": true, "sortable": true }, { "key": "bf16_tflops", "label": "BF16", "type": "number", "unit": "TFLOPS", "description": "Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "fp16_tflops", "label": "FP16", "type": "number", "unit": "TFLOPS", "description": "Published FP16 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "mxfp8_tflops", "label": "MXFP8", "type": "number", "unit": "TFLOPS", "description": "Published MXFP8 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "mxfp4_tflops", "label": "MXFP4", "type": "number", "unit": "TFLOPS", "description": "Published MXFP4 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "mx8_tflops", "label": "MX8", "type": "number", "unit": "TFLOPS", "description": "Published MX8 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "mx4_tflops", "label": "MX4", "type": "number", "unit": "TFLOPS", "description": "Published MX4 throughput per chip or accelerator module in TFLOPS. See the precision note for shared-format figures, sparsity and module scope.", "filterable": true, "sortable": true }, { "key": "fp8_tflops", "label": "FP8", "type": "number", "unit": "TFLOPS", "description": "Published peak FP8 throughput per chip in TFLOPS. The precision note records sparsity where the owner states it. Blank when the owner gives no FP8 figure.", "filterable": true, "sortable": true }, { "key": "int8_tops", "label": "INT8", "type": "number", "unit": "TOPS", "description": "Peak INT8 throughput per chip in TOPS, as published. Mostly given for inference chips.", "filterable": false, "sortable": true }, { "key": "fp4_tflops", "label": "FP4", "type": "number", "unit": "TFLOPS", "description": "Published FP4 throughput per chip or accelerator module in TFLOPS. MXFP4 and MX4 have separate columns; see the precision note for scope.", "filterable": false, "sortable": true }, { "key": "peak_note", "label": "Precision note", "type": "string", "description": "What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.", "filterable": false, "sortable": false }, { "key": "cpu_cores", "label": "CPU cores", "type": "number", "description": "Cores per socket, for server CPUs.", "filterable": false, "sortable": true }, { "key": "tdp_w", "label": "Power", "type": "number", "unit": "W", "description": "Chip or package power in watts as published (TDP, TBP or typical power; the source says which).", "filterable": false, "sortable": true }, { "key": "pod_chips", "label": "Largest pod", "type": "number", "unit": "chips", "description": "The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.", "filterable": true, "sortable": true }, { "key": "status", "label": "Status", "type": "enum", "description": "Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.", "filterable": true, "sortable": true, "enumValues": [ "Announced", "Sampling", "Preview", "Deployed", "Discontinued" ] }, { "key": "announced_year", "label": "Announced", "type": "number", "description": "Year the owner first announced the chip publicly.", "filterable": true, "sortable": true }, { "key": "deployment_scale", "label": "Deployment scale", "type": "string", "description": "The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.", "filterable": false, "sortable": false }, { "key": "available_as", "label": "How to get it", "type": "string", "description": "How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.", "filterable": false, "sortable": false } ], "records": [ { "id": "alibaba-zhenwu-810e", "name": "Alibaba T-Head Zhenwu 810E", "url": "https://help.aliyun.com/en/document_detail/2864586.html", "summary": "Alibaba's in-house AI accelerator (the T-Head PPU): 96 GB of HBM2e at 2.77 TB/s, 700 GB/s chip-to-chip links and 400 W, running in 10,000-card clusters on Alibaba Cloud for more than 400 customers.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Alibaba", "role": "Training and inference", "design_partner": "In-house (T-Head)", "foundry": null, "process_node": null, "hbm_type": "HBM2e", "hbm_gb": 96, "mem_bw_tbs": 2.77, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "No FLOPS figure published; T-Head positions it against NVIDIA's H20.", "cpu_cores": null, "tdp_w": 400, "pod_chips": null, "status": "Deployed", "announced_year": 2026, "deployment_scale": "Deployed in 10,000-card clusters on Alibaba Cloud (January 2026); Zhenwu shipments reached 560,000 units by May 2026.", "available_as": "Alibaba Cloud PAI and ACK Lingjun PPU clusters" }, "sources": [ { "url": "https://help.aliyun.com/en/document_detail/2864586.html", "title": "Alibaba Cloud: PPU-ZHENWU PPU cloud service", "accessed": "2026-11-11", "fields": [ "owner", "hbm_type", "hbm_gb", "mem_bw_tbs", "tdp_w", "available_as" ] }, { "url": "https://technode.com/2026/01/30/alibabas-t-head-unveils-self-developed-ai-chip-zhenwu-810e/", "title": "TechNode: Alibaba's T-Head unveils self-developed AI chip Zhenwu 810E", "accessed": "2026-11-11", "fields": [ "role", "design_partner", "peak_note", "status", "announced_year", "deployment_scale" ] }, { "url": "https://www.trendforce.com/news/2026/05/21/news-alibaba-t-head-unveils-zhenwu-m890-with-3x-performance-vs-prior-gen-new-ai-chips-planned-for-3q273q28/", "title": "TrendForce: Alibaba T-Head unveils Zhenwu M890", "accessed": "2026-11-11", "fields": [ "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "alibaba-zhenwu-m890", "name": "Alibaba T-Head Zhenwu M890", "url": "https://www.trendforce.com/news/2026/05/21/news-alibaba-t-head-unveils-zhenwu-m890-with-3x-performance-vs-prior-gen-new-ai-chips-planned-for-3q273q28/", "summary": "T-Head's 2026 accelerator: 144 GB of HBM, 800 GB/s chip-to-chip links and three times the 810E's performance, shown at Alibaba Cloud Summit with a 128-chip supernode server. The V900 follows in 3Q27.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Alibaba", "role": "Training and inference", "design_partner": "In-house (T-Head)", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 144, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "No FLOPS figure published; T-Head states three times the Zhenwu 810E's performance.", "cpu_cores": null, "tdp_w": null, "pod_chips": 128, "status": "Announced", "announced_year": 2026, "deployment_scale": null, "available_as": null }, "sources": [ { "url": "https://www.trendforce.com/news/2026/05/21/news-alibaba-t-head-unveils-zhenwu-m890-with-3x-performance-vs-prior-gen-new-ai-chips-planned-for-3q273q28/", "title": "TrendForce: Alibaba T-Head unveils Zhenwu M890 with 3x performance", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "hbm_type", "hbm_gb", "peak_note", "pod_chips", "status", "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-graviton4", "name": "AWS Graviton4", "url": "https://aws.amazon.com/ec2/graviton/", "summary": "Amazon's fourth Arm server CPU: 96 cores per socket and DDR5-5600 memory, generally available in EC2 R8g instances since July 2024 and paired with Trainium in AWS AI racks.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Server CPU", "design_partner": "In-house (Annapurna Labs)", "foundry": null, "process_node": null, "hbm_type": "DDR5-5600", "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": 96, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2023, "deployment_scale": "AWS has built more than 2 million Graviton processors across generations (AWS, July 2024).", "available_as": "AWS EC2 R8g, M8g, C8g and X8g instances" }, "sources": [ { "url": "https://aws.amazon.com/blogs/aws/aws-graviton4-based-amazon-ec2-r8g-instances-best-price-performance-in-amazon-ec2", "title": "AWS News Blog: Graviton4-based EC2 R8g instances generally available", "accessed": "2026-11-11", "fields": [ "owner", "role", "status", "announced_year", "deployment_scale", "available_as" ] }, { "url": "https://www.theregister.com/2025/12/04/amazon_graviton_5/", "title": "The Register: Amazon keeps the pressure on Intel, AMD with 192-core Graviton5", "accessed": "2026-11-11", "fields": [ "cpu_cores" ] }, { "url": "https://aws.amazon.com/blogs/aws/amazon-ec2-r9g-and-r9gd-instances-powered-by-aws-graviton5-processors-are-now-generally-available/", "title": "AWS News Blog: EC2 R9g and R9gd instances powered by Graviton5", "accessed": "2026-11-11", "fields": [ "hbm_type" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "design_partner" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-graviton5", "name": "AWS Graviton5", "url": "https://aws.amazon.com/ec2/graviton/", "summary": "Amazon's fifth Arm server CPU: 192 Neoverse V3 cores on TSMC 3 nm in one socket, a 5x larger L3 cache than Graviton4 and DDR5-8800 memory, generally available in EC2 M9g, C9g and R9g instances in 2026.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Server CPU", "design_partner": "In-house (Annapurna Labs)", "foundry": "TSMC", "process_node": "TSMC 3 nm", "hbm_type": "DDR5-8800", "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": 192, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2025, "deployment_scale": "Graviton has been more than half of all new AWS CPU capacity for three years running (AWS, December 2025); over 120,000 AWS customers use Graviton.", "available_as": "AWS EC2 M9g, C9g, R9g and R9gd instances" }, "sources": [ { "url": "https://www.theregister.com/2025/12/04/amazon_graviton_5/", "title": "The Register: Amazon keeps the pressure on Intel, AMD with 192-core Graviton5", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "cpu_cores", "announced_year", "deployment_scale" ] }, { "url": "https://aws.amazon.com/blogs/aws/amazon-ec2-r9g-and-r9gd-instances-powered-by-aws-graviton5-processors-are-now-generally-available/", "title": "AWS News Blog: EC2 R9g and R9gd instances powered by Graviton5 now generally available", "accessed": "2026-11-11", "fields": [ "hbm_type", "status", "available_as" ] }, { "url": "https://aws.amazon.com/ec2/graviton/", "title": "AWS: Graviton processors", "accessed": "2026-11-11", "fields": [ "deployment_scale" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "design_partner" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-inferentia", "name": "AWS Inferentia", "url": "https://aws.amazon.com/ec2/instance-types/inf1/", "summary": "Amazon's first in-house machine learning chip, announced at re:Invent 2018: four NeuronCores, 128 INT8 TOPS and 8 GB of on-board DRAM, sold through EC2 Inf1 instances with up to 16 chips.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Inference", "design_partner": "In-house (Annapurna Labs)", "foundry": null, "process_node": null, "hbm_type": "DRAM (not HBM)", "hbm_gb": 8, "mem_bw_tbs": 0.05, "bf16_tflops": 64, "fp8_tflops": null, "int8_tops": 128, "fp4_tflops": null, "peak_note": "AWS lists 128 INT8 TOPS and 64 FP16/BF16 TFLOPS per chip, with 8 GB of device DRAM at 50 GB/s.", "cpu_cores": null, "tdp_w": null, "pod_chips": 16, "status": "Deployed", "announced_year": 2018, "deployment_scale": null, "available_as": "AWS EC2 Inf1 instances" }, "sources": [ { "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/v2.9.1/general/arch/neuron-hardware/inferentia.html", "title": "AWS Neuron docs: Inferentia architecture", "accessed": "2026-11-11", "fields": [ "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "role" ] }, { "url": "https://aws.amazon.com/blogs/aws/amazon-ec2-update-inf1-instances-with-aws-inferentia-chips-for-high-performance-cost-effective-inferencing", "title": "AWS News Blog: Inf1 instances with AWS Inferentia chips", "accessed": "2026-11-11", "fields": [ "owner", "pod_chips", "status", "available_as" ] }, { "url": "https://aws.amazon.com/ec2/instance-types/inf1/", "title": "AWS: Amazon EC2 Inf1 instances", "accessed": "2026-11-11", "fields": [ "announced_year" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "design_partner" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-inferentia2", "name": "AWS Inferentia2", "url": "https://aws.amazon.com/ai/machine-learning/inferentia/", "summary": "Amazon's second inference chip: 32 GB of HBM, 190 FP16/BF16 TFLOPS and 380 INT8 TOPS per chip, rented through EC2 Inf2 instances.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Inference", "design_partner": "In-house (Annapurna Labs)", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 32, "mem_bw_tbs": 0.88, "bf16_tflops": 190, "fp8_tflops": null, "int8_tops": 380, "fp4_tflops": null, "peak_note": "AWS gives one shared figure of 190 TFLOPS for FP16, BF16, cFP8 and TF32, plus 380 INT8 TOPS and 47.5 FP32 TFLOPS. Memory bandwidth is 820 GiB/s (0.88 TB/s).", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2022, "deployment_scale": null, "available_as": "AWS EC2 Inf2 instances" }, "sources": [ { "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/latest/about-neuron/arch/neuron-hardware/inferentia2.html", "title": "AWS Neuron docs: Inferentia2 architecture", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "status", "available_as" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "design_partner" ] }, { "url": "https://aws.amazon.com/blogs/aws/amazon-ec2-inf2-instances-for-low-cost-high-performance-generative-ai-inference-are-now-generally-available/", "title": "AWS: Inf2 GA announcement recalls re:Invent 2022 preview", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-trainium", "name": "AWS Trainium", "url": "https://aws.amazon.com/ai/machine-learning/trainium/", "summary": "Amazon's first training chip: 32 GB of HBM and 190 BF16 TFLOPS per chip, with 16 chips in each EC2 Trn1 instance.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Training", "design_partner": "In-house (Annapurna Labs)", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 32, "mem_bw_tbs": 0.82, "bf16_tflops": 190, "fp8_tflops": null, "int8_tops": 380, "fp4_tflops": null, "peak_note": "AWS gives one shared figure of 190 TFLOPS for FP16, BF16, cFP8 and TF32, plus 47.5 FP32 TFLOPS and 380 INT8 TOPS. Memory bandwidth is 820 GiB/s.", "cpu_cores": null, "tdp_w": null, "pod_chips": 16, "status": "Deployed", "announced_year": 2020, "deployment_scale": null, "available_as": "AWS EC2 Trn1 instances" }, "sources": [ { "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/latest/about-neuron/arch/neuron-hardware/trainium.html", "title": "AWS Neuron docs: Trainium architecture", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "pod_chips", "status", "available_as" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "design_partner" ] }, { "url": "https://ir.aboutamazon.com/news-release/news-release-details/2021/Amazon.com-Announces-Fourth-Quarter-Results/default.aspx", "title": "Amazon: Q4 2020 results, Trainium announced during the quarter", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-trainium2", "name": "AWS Trainium2", "url": "https://aws.amazon.com/ai/machine-learning/trainium/", "summary": "The chip behind Project Rainier: 96 GiB of HBM, 1,299 FP8 TFLOPS per chip, 64 chips per Trn2 UltraServer and nearly 500,000 chips in the Rainier cluster that Anthropic uses to build and deploy Claude.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Training and inference", "design_partner": "In-house (Annapurna Labs)", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 96, "mem_bw_tbs": 2.9, "bf16_tflops": 667, "fp8_tflops": 1299, "int8_tops": null, "fp4_tflops": null, "peak_note": "Per chip: 1,299 FP8 TFLOPS and 667 BF16/FP16/TF32 TFLOPS. AWS lists 2,563 TFLOPS separately as sparse, not used here.", "cpu_cores": null, "tdp_w": null, "pod_chips": 64, "status": "Deployed", "announced_year": 2023, "deployment_scale": "Project Rainier: nearly 500,000 Trainium2 chips live in October 2025; Anthropic’s Claude now runs on more than one million Trainium2 chips (Amazon).", "available_as": "AWS EC2 Trn2 instances and Trn2 UltraServers" }, "sources": [ { "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/latest/about-neuron/arch/neuron-hardware/trainium2.html", "title": "AWS Neuron docs: Trainium2 architecture", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "fp8_tflops", "peak_note" ] }, { "url": "https://www.aboutamazon.com/news/aws/aws-project-rainier-ai-trainium-chips-compute-cluster", "title": "Amazon: Project Rainier, one of the world's largest AI compute clusters", "accessed": "2026-11-11", "fields": [ "pod_chips", "status", "deployment_scale", "available_as" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-ai-chips-business-history", "title": "Amazon: How Amazon became one of the world's top chip companies in a decade", "accessed": "2026-11-11", "fields": [ "deployment_scale", "design_partner" ] }, { "url": "https://press.aboutamazon.com/2023/11/aws-unveils-next-generation-aws-designed-chips", "title": "Amazon: AWS unveils Graviton4 and Trainium2, November 28, 2023", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-trainium3", "name": "AWS Trainium3", "url": "https://aws.amazon.com/ai/machine-learning/trainium/", "summary": "Amazon's first 3 nm AI chip: 144 GB of HBM3E at 4.9 TB/s and 2,517 MXFP8 TFLOPS per chip, with 144 chips per Trn3 UltraServer. Generally available since December 2025, with customers including Anthropic.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Training and inference", "design_partner": "Alchip; Marvell", "foundry": null, "process_node": "3 nm", "hbm_type": "HBM3E", "hbm_gb": 144, "mem_bw_tbs": 4.9, "bf16_tflops": 671, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Per chip: 2,517 TFLOPS MXFP8 and MXFP4, 671 BF16/FP16/TF32 TFLOPS (AWS Neuron docs; dense or sparse not labelled for these). A 144-chip UltraServer delivers 362 FP8 PFLOPS (AWS figure).", "cpu_cores": null, "tdp_w": null, "pod_chips": 144, "status": "Deployed", "announced_year": 2024, "deployment_scale": "EC2 UltraClusters 3.0 connect up to 1 million Trainium chips (AWS, December 2025).", "available_as": "AWS EC2 Trn3 UltraServers; Amazon Bedrock", "mxfp8_tflops": 2517, "mxfp4_tflops": 2517, "partner_basis": "Reported by TrendForce (October 2025): Trainium3 developed jointly with Alchip and Marvell. AWS has not confirmed." }, "sources": [ { "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/latest/about-neuron/arch/neuron-hardware/trainium3.html", "title": "AWS Neuron docs: Trainium3 architecture", "accessed": "2026-11-11", "fields": [ "owner", "role", "bf16_tflops", "mxfp8_tflops", "mxfp4_tflops", "peak_note" ] }, { "url": "https://www.aboutamazon.com/news/aws/trainium-3-ultraserver-faster-ai-training-lower-cost", "title": "Amazon: Trainium3 UltraServers now available", "accessed": "2026-11-11", "fields": [ "process_node", "pod_chips", "status", "deployment_scale", "available_as" ] }, { "url": "https://aws.amazon.com/about-aws/whats-new/2025/12/amazon-ec2-trn3-ultraservers", "title": "AWS What's New: Amazon EC2 Trn3 UltraServers", "accessed": "2026-11-11", "fields": [ "hbm_type", "hbm_gb", "mem_bw_tbs", "process_node" ] }, { "url": "https://www.trendforce.com/news/2025/10/31/news-awss-trainium3-reportedly-draws-strong-interest-from-large-mid-sized-clients-ramping-early-26/", "title": "TrendForce: AWS's Trainium3 draws strong interest, ramping early 2026", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] }, { "url": "https://www.aboutamazon.com/news/aws/amazon-nova-ai-canvas-reel-aws-reinvent", "title": "Amazon: re:Invent 2024 announcements include Trainium3", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "aws-trainium4", "name": "AWS Trainium4", "url": "https://www.aboutamazon.com/news/aws/trainium-3-ultraserver-faster-ai-training-lower-cost", "summary": "AWS announced Trainium4 alongside Trainium3 in December 2025. Its roadmap targets at least six times Trainium3’s FP4 compute and four times its memory bandwidth, with delivery expected in 2027.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Amazon Web Services", "role": "Training and inference", "design_partner": null, "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "AWS roadmap targets at least 6x FP4 compute, 3x FP8 compute and 4x memory bandwidth versus Trainium3. Absolute TFLOPS are not published; no values are inferred from ratios.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2025, "deployment_scale": "Expected to start delivering in 2027 (Amazon Q4 2025 earnings release).", "available_as": null }, "sources": [ { "url": "https://www.aboutamazon.com/news/aws/trainium-3-ultraserver-faster-ai-training-lower-cost", "title": "Amazon: Trainium3 launch and Trainium4 roadmap", "accessed": "2026-11-11", "fields": [ "owner", "role", "status", "announced_year", "peak_note" ] }, { "url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000002/amzn-20251231xex991.htm", "title": "Amazon Q4 2025 earnings release: Trainium4 delivery expected in 2027", "accessed": "2026-11-11", "fields": [ "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "baidu-kunlun-m100", "name": "Baidu Kunlunxin M100", "url": "https://www.kunlunxin.com/", "summary": "Baidu unveiled Kunlun M100 at Baidu World in November 2025 for large-scale inference, including mixture-of-experts models. The announced launch target is early 2026; a target date alone is not evidence of deployment.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Baidu", "role": "Inference", "design_partner": "In-house (Kunlunxin)", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2025, "deployment_scale": "Roadmap launch target: early 2026. Customer deployment not verified.", "available_as": null }, "sources": [ { "url": "https://www.scmp.com/tech/big-tech/article/3332596/baidu-unveils-ai-chips-boost-chinas-self-sufficiency-drive", "title": "SCMP: original reporting from Baidu World, November 13, 2025", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "deployment_scale" ] }, { "url": "https://www.dbs.com.sg/treasures/aics/templatedata/article/recentdevelopment/data/en/DBSV/012021/9888_HK_11142025.xml", "title": "DBS: attended Baidu World 2025 and investor forum; M100/M300 roadmap", "accessed": "2026-11-11", "fields": [ "announced_year", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "baidu-kunlun-m300", "name": "Baidu Kunlunxin M300", "url": "https://www.kunlunxin.com/", "summary": "Baidu unveiled Kunlun M300 at Baidu World in November 2025 for training and inference of large multimodal models. The announced launch target is early 2027; a target date alone is not evidence of deployment.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Baidu", "role": "Training and inference", "design_partner": "In-house (Kunlunxin)", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2025, "deployment_scale": "Roadmap launch target: early 2027. Customer deployment not verified.", "available_as": null }, "sources": [ { "url": "https://www.scmp.com/tech/big-tech/article/3332596/baidu-unveils-ai-chips-boost-chinas-self-sufficiency-drive", "title": "SCMP: original reporting from Baidu World, November 13, 2025", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "deployment_scale" ] }, { "url": "https://www.dbs.com.sg/treasures/aics/templatedata/article/recentdevelopment/data/en/DBSV/012021/9888_HK_11142025.xml", "title": "DBS: attended Baidu World 2025 and investor forum; M100/M300 roadmap", "accessed": "2026-11-11", "fields": [ "announced_year", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "baidu-kunlun-p800", "name": "Baidu Kunlunxin P800", "url": "https://www.kunlunxin.com/", "summary": "Baidu's third-generation Kunlun chip: 96 GB of HBM and 345 FP16 TFLOPS. Baidu powered up a 30,000-chip P800 cluster in April 2025 to train DeepSeek-class models, and it packs 256 of them into one Tianchi supernode.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Baidu", "role": "Training and inference", "design_partner": "In-house (Kunlunxin)", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 96, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "345 TFLOPS is Kunlunxin's FP16 figure; the chip also supports FP8 and FP32.", "cpu_cores": null, "tdp_w": null, "pod_chips": 256, "status": "Deployed", "announced_year": null, "deployment_scale": "30,000-chip P800 cluster switched on in April 2025 (Baidu CEO Robin Li, via Reuters).", "available_as": "Baidu AI Cloud (Baige platform)", "fp16_tflops": 345 }, "sources": [ { "url": "https://udn.com/news/story/7333/9639904", "title": "UDN: Kunlunxin shows M100 and P800 at WAIC 2026", "accessed": "2026-11-11", "fields": [ "owner", "design_partner", "hbm_type", "hbm_gb", "fp16_tflops", "peak_note", "status" ] }, { "url": "https://finance.yahoo.com/news/baidu-launches-ai-model-amid-021731378.html", "title": "Reuters: China's Baidu says its Kunlun chip cluster can train DeepSeek-like models", "accessed": "2026-11-11", "fields": [ "role", "deployment_scale" ] }, { "url": "https://www.trendforce.com/news/2025/11/13/news-baidu-rolls-out-kunlun-roadmap-m100-m300-ai-chips-arrive-2026-2027/", "title": "TrendForce: Baidu rolls out Kunlun roadmap, Tianchi supernodes", "accessed": "2026-11-11", "fields": [ "pod_chips", "available_as" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-axion", "name": "Google Axion", "url": "https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu", "summary": "Axion is Google's first custom Arm data center CPU, built on Neoverse V2, with up to 50% better performance and 60% better energy efficiency than comparable x86 instances. It runs Google services such as Bigtable, Spanner, BigQuery and YouTube Ads.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Server CPU", "design_partner": null, "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Arm Neoverse V2 cores; C4A VMs scale to 72 vCPUs (each a full core, no SMT) and C4A metal to 96 vCPUs. Google does not publish a per-chip core count.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2024, "deployment_scale": "In production inside Google for Bigtable, Spanner, BigQuery and YouTube Ads (The Next Platform, Apr 2024)", "available_as": "Google Cloud C4A VMs and C4A metal" }, "sources": [ { "url": "https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu", "title": "Google Cloud Blog: Introducing Google Axion Processors, our new Arm-based CPUs", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "status", "available_as" ] }, { "url": "https://docs.cloud.google.com/compute/docs/instances/arm-on-compute", "title": "Google Cloud: Arm VMs on Compute", "accessed": "2026-11-11", "fields": [ "peak_note", "available_as" ] }, { "url": "https://www.nextplatform.com/2024/04/09/google-joins-the-homegrown-arm-server-cpu-club", "title": "The Next Platform: Google joins the homegrown Arm server CPU club", "accessed": "2026-11-11", "fields": [ "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-8i", "name": "Google TPU 8i", "url": "https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive", "summary": "TPU 8i is Google's eighth-generation inference chip for sampling, serving and reasoning, with 288 GB of HBM at 8.6 TB/s and 384 MB of on-chip SRAM. Google rates it at up to 80% better inference price-performance than Ironwood.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 288, "mem_bw_tbs": 8.601, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": 10100, "peak_note": "Google states 10.1 PFLOPS peak FP4 per chip; no FP8 or BF16 figure published. 384 MB on-chip SRAM, Boardfly topology, Arm Axion host. Up to 1,152 chips connected (1,024 active per pod). TPU 8i Max (Nov 2026) puts two 8i chips on one package.", "cpu_cores": null, "tdp_w": null, "pod_chips": 1152, "status": "Announced", "announced_year": 2026, "deployment_scale": null, "available_as": null, "partner_basis": "Stated by Broadcom CEO Hock Tan on Broadcom's Q3 FY2026 earnings call (Motley Fool transcript): Broadcom ships TPU 8i, MediaTek builds TPU 8t. Google has not confirmed." }, "sources": [ { "url": "https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive", "title": "Google Cloud Blog: TPU 8t and TPU 8i technical deep dive", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "status", "hbm_gb", "mem_bw_tbs", "fp4_tflops", "peak_note", "pod_chips" ] }, { "url": "https://blog.google/innovation-and-ai/infrastructure-and-cloud/global-network/tpu-8i-max-and-8tx/", "title": "Google: Our newest TPUs: 8tx and 8i Max, built for the agentic era", "accessed": "2026-11-11", "fields": [ "peak_note" ] }, { "url": "https://www.fool.com/earnings/call-transcripts/2026/09/09/broadcom-avgo-q3-2026-earnings-call-transcript/", "title": "Broadcom Q3 FY2026 earnings call: Hock Tan names Broadcom TPU 8i and MediaTek v8t", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-8t", "name": "Google TPU 8t", "url": "https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive", "summary": "TPU 8t is Google's eighth-generation training chip, with 12.6 PFLOPS FP4 and 216 GB of HBM per chip, 9,600 chips per superpod and over 134,000 chips on one Virgo fabric. Google rates it at up to 2.7x the training price-performance of Ironwood.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training", "design_partner": "MediaTek", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 216, "mem_bw_tbs": 6.528, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": 12600, "peak_note": "Google states 12.6 PFLOPS peak FP4 per chip; no FP8 or BF16 figure published. 128 MB on-chip SRAM, Arm Axion host CPU. TPU 8tx (Nov 2026) uses the same silicon with AMD EPYC hosts.", "cpu_cores": null, "tdp_w": null, "pod_chips": 9600, "status": "Announced", "announced_year": 2026, "deployment_scale": "Virgo network links over 134,000 TPU 8t chips in one fabric (Google, Apr 2026)", "available_as": null, "partner_basis": "Stated by Broadcom CEO Hock Tan on Broadcom's Q3 FY2026 earnings call (Motley Fool transcript): Broadcom ships TPU 8i, MediaTek builds TPU 8t. Google has not confirmed." }, "sources": [ { "url": "https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive", "title": "Google Cloud Blog: TPU 8t and TPU 8i technical deep dive", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "status", "hbm_gb", "mem_bw_tbs", "fp4_tflops", "peak_note", "pod_chips", "deployment_scale" ] }, { "url": "https://blog.google/innovation-and-ai/infrastructure-and-cloud/global-network/tpu-8i-max-and-8tx/", "title": "Google: Our newest TPUs: 8tx and 8i Max, built for the agentic era", "accessed": "2026-11-11", "fields": [ "peak_note" ] }, { "url": "https://www.fool.com/earnings/call-transcripts/2026/09/09/broadcom-avgo-q3-2026-earnings-call-transcript/", "title": "Broadcom Q3 FY2026 earnings call: Hock Tan names Broadcom TPU 8i and MediaTek v8t", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-v4", "name": "Google TPU v4", "url": "https://docs.cloud.google.com/tpu/docs/v4", "summary": "Google's fourth-generation TPU links 4,096 chips per pod through optical circuit switches for more than one exaflop of BF16 compute. Each chip delivers 275 TFLOPS BF16/INT8 with 32 GiB of HBM2.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": "HBM2", "hbm_gb": 32, "mem_bw_tbs": 1.2, "bf16_tflops": 275, "fp8_tflops": null, "int8_tops": 275, "fp4_tflops": null, "peak_note": "Google lists 275 TFLOPS 'bf16 or int8' per chip. Measured min/mean/max power 90/170/192 W; no TDP published.", "cpu_cores": null, "tdp_w": null, "pod_chips": 4096, "status": "Deployed", "announced_year": 2021, "deployment_scale": "Operational at Google since 2020; dozens of 4,096-chip pods planned for Google data centers (Google, 2021)", "available_as": "Google Cloud TPU v4", "partner_basis": "Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed." }, "sources": [ { "url": "https://docs.cloud.google.com/tpu/docs/v4", "title": "Google Cloud: TPU v4", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "pod_chips", "status", "available_as" ] }, { "url": "https://blog.google/intl/en-in/company-news/inside-google/google-io-2021-being-helpful-moments-matter/", "title": "Google: Google I/O 2021: Being helpful in moments that matter", "accessed": "2026-11-11", "fields": [ "owner", "announced_year", "deployment_scale" ] }, { "url": "https://cloud.google.com/blog/topics/systems/tpu-v4-enables-performance-energy-and-co2e-efficiency-gains", "title": "Google Cloud Blog: TPU v4 provides exaFLOPS-scale ML with industry-leading efficiency", "accessed": "2026-11-11", "fields": [ "deployment_scale", "status", "pod_chips" ] }, { "url": "https://arxiv.org/abs/2304.01433", "title": "arXiv (ISCA 2023): TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning", "accessed": "2026-11-11", "fields": [ "pod_chips", "status" ] }, { "url": "https://www.thestar.com.my/tech/tech-news/2025/03/17/google-preparing-to-partner-with-taiwan039s-mediatek-on-next-ai-chip-information-reports", "title": "Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-v5e", "name": "Google TPU v5e", "url": "https://cloud.google.com/blog/products/compute/announcing-cloud-tpu-v5e-and-a3-gpus-in-ga/", "summary": "Google's cost-optimized TPU for training and serving, with 197 TFLOPS BF16 and 393 TOPS INT8 per chip in 256-chip pods. Google rates it at up to 2.5x the inference performance per dollar of TPU v4.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 16, "mem_bw_tbs": 0.8, "bf16_tflops": 197, "fp8_tflops": null, "int8_tops": 393, "fp4_tflops": null, "peak_note": "Dense per-chip peaks. Google lists HBM bandwidth as 800 GiBps.", "cpu_cores": null, "tdp_w": null, "pod_chips": 256, "status": "Deployed", "announced_year": 2023, "deployment_scale": null, "available_as": "Google Cloud TPU v5e", "partner_basis": "Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed." }, "sources": [ { "url": "https://docs.cloud.google.com/tpu/docs/v5e", "title": "Google Cloud: TPU v5e", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "pod_chips", "status", "available_as" ] }, { "url": "https://cloud.google.com/blog/products/compute/announcing-cloud-tpu-v5e-and-a3-gpus-in-ga/", "title": "Google Cloud Blog: Announcing Cloud TPU v5e and A3 GPUs", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "pod_chips" ] }, { "url": "https://www.thestar.com.my/tech/tech-news/2025/03/17/google-preparing-to-partner-with-taiwan039s-mediatek-on-next-ai-chip-information-reports", "title": "Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-v5p", "name": "Google TPU v5p", "url": "https://cloud.google.com/blog/products/ai-machine-learning/introducing-cloud-tpu-v5p-and-ai-hypercomputer", "summary": "Google's performance TPU, launched in December 2023 with 8,960 chips per pod and 459 TFLOPS BF16 per chip. Google says it trains large LLMs 2.8x faster per chip than TPU v4.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 95, "mem_bw_tbs": 2.765, "bf16_tflops": 459, "fp8_tflops": 459, "int8_tops": null, "fp4_tflops": null, "peak_note": "Per-chip peaks from Google's TPU v5p docs, which list 459 TFLOPS for both BF16 and FP8. HBM: 95 GiB allocatable of 96 GiB physical.", "cpu_cores": null, "tdp_w": null, "pod_chips": 8960, "status": "Deployed", "announced_year": 2023, "deployment_scale": "Salesforce and Lightricks named as early customers (Google, Dec 2023)", "available_as": "Google Cloud TPU v5p", "partner_basis": "Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed." }, "sources": [ { "url": "https://docs.cloud.google.com/tpu/docs/v5p", "title": "Google Cloud: TPU v5p", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "fp8_tflops", "peak_note", "pod_chips", "status", "available_as" ] }, { "url": "https://cloud.google.com/blog/products/ai-machine-learning/introducing-cloud-tpu-v5p-and-ai-hypercomputer", "title": "Google Cloud Blog: Enabling next-generation AI workloads: Announcing TPU v5p and AI Hypercomputer", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "pod_chips", "deployment_scale" ] }, { "url": "https://www.thestar.com.my/tech/tech-news/2025/03/17/google-preparing-to-partner-with-taiwan039s-mediatek-on-next-ai-chip-information-reports", "title": "Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-v6e-trillium", "name": "Google TPU v6e Trillium", "url": "https://cloud.google.com/blog/products/compute/trillium-tpu-is-ga", "summary": "Trillium, Google's sixth-generation TPU, delivers 918 TFLOPS BF16 per chip, a 4.7x jump in peak compute, and trained Gemini 2.0. Google scales it past 100,000 chips on one Jupiter network fabric.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 32, "mem_bw_tbs": 1.638, "bf16_tflops": 918, "fp8_tflops": null, "int8_tops": 1836, "fp4_tflops": null, "peak_note": "Per-chip peaks from Google's docs; Google does not label them dense or sparse. No FP8 figure published.", "cpu_cores": null, "tdp_w": null, "pod_chips": 256, "status": "Deployed", "announced_year": 2024, "deployment_scale": "Over 100,000 Trillium chips per Jupiter network fabric; used to train Gemini 2.0 (Google, Dec 2024)", "available_as": "Google Cloud TPU v6e", "partner_basis": "Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed." }, "sources": [ { "url": "https://docs.cloud.google.com/tpu/docs/v6e", "title": "Google Cloud: TPU v6e", "accessed": "2026-11-11", "fields": [ "owner", "role", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "pod_chips", "status", "available_as" ] }, { "url": "https://cloud.google.com/blog/products/compute/trillium-tpu-is-ga", "title": "Google Cloud Blog: Announcing the general availability of Trillium, our sixth-generation TPU", "accessed": "2026-11-11", "fields": [ "owner", "role", "status", "announced_year", "deployment_scale", "available_as" ] }, { "url": "https://www.thestar.com.my/tech/tech-news/2025/03/17/google-preparing-to-partner-with-taiwan039s-mediatek-on-next-ai-chip-information-reports", "title": "Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports", "accessed": "2026-11-11", "fields": [ "design_partner", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "google-tpu-v7-ironwood", "name": "Google TPU v7 Ironwood", "url": "https://blog.google/products/google-cloud/ironwood-tpu-age-of-inference/", "summary": "Ironwood, Google's seventh-generation TPU, packs 4,614 TFLOPS FP8 and 192 GB of HBM per chip and scales to 9,216 liquid-cooled chips in one superpod. Anthropic plans to access up to 1 million TPUs, and Broadcom's CEO said Broadcom took a $10 billion order to sell Ironwood racks to Anthropic.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Google", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": 192, "mem_bw_tbs": 7.37, "bf16_tflops": 2307, "fp8_tflops": 4614, "int8_tops": null, "fp4_tflops": null, "peak_note": "Per-chip figures: Google states 4,614 TFLOPS FP8 and 2,307 TFLOPS BF16 and does not label them dense or sparse. Two chiplets with 96 GiB HBM each.", "cpu_cores": null, "tdp_w": null, "pod_chips": 9216, "status": "Deployed", "announced_year": 2025, "deployment_scale": "Anthropic plans to access up to 1 million TPUs (Google, Nov 2025); Broadcom took a $10B order to sell Ironwood racks to Anthropic (Broadcom CEO, Dec 2025)", "available_as": "Google Cloud TPU7x (Ironwood)", "partner_basis": "Reported by CNBC: Broadcom's CEO said Broadcom sells Ironwood TPU racks to Anthropic. Google has not named a design partner." }, "sources": [ { "url": "https://blog.google/products/google-cloud/ironwood-tpu-age-of-inference/", "title": "Google: Ironwood: The first Google TPU for the age of inference", "accessed": "2026-11-11", "fields": [ "owner", "role", "announced_year", "hbm_gb", "mem_bw_tbs", "fp8_tflops", "pod_chips" ] }, { "url": "https://docs.cloud.google.com/tpu/docs/tpu7x", "title": "Google Cloud: TPU7x (Ironwood)", "accessed": "2026-11-11", "fields": [ "bf16_tflops", "fp8_tflops", "hbm_gb", "mem_bw_tbs", "pod_chips", "peak_note", "status", "available_as" ] }, { "url": "https://cloud.google.com/blog/products/compute/ironwood-tpus-and-new-axion-based-vms-for-your-ai-workloads", "title": "Google Cloud Blog: Ironwood TPUs and new Axion-based VMs for your AI workloads", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale", "pod_chips" ] }, { "url": "https://www.cnbc.com/2025/12/11/broadcom-reveals-its-mystery-10-billion-customer-is-anthropic.html", "title": "CNBC: Broadcom reveals its mystery $10 billion customer is Anthropic", "accessed": "2026-11-11", "fields": [ "design_partner", "deployment_scale", "partner_basis" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-910b", "name": "Huawei Ascend 910B", "url": "https://www.hiascend.com/", "summary": "Huawei's workhorse AI chip in China since 2023: 64 GB of HBM2e at 1.6 TB/s on SMIC's 7 nm (N+2) process, rented through Huawei Cloud and bought by Baidu, Tencent and iFLYTEK.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Training and inference", "design_partner": "In-house (HiSilicon)", "foundry": "SMIC", "process_node": "SMIC 7 nm (N+2)", "hbm_type": "HBM2e", "hbm_gb": 64, "mem_bw_tbs": 1.6, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "400 FP16 TFLOPS and 64 GB HBM, stated in the Huawei Cloud co-authored DeepServe paper (USENIX ATC 2025, section 2). CSET independently estimates about 400 FP16 TFLOPS for the fastest variant; variants differ.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2022, "deployment_scale": "Bought by Baidu, Tencent and iFLYTEK (CSET, 2024).", "available_as": "Huawei Cloud; Atlas servers", "fp16_tflops": 400 }, "sources": [ { "url": "https://www.usenix.org/system/files/atc25-hu-junhao.pdf", "title": "DeepServe: Serverless Large Language Model Serving at Scale, section 2 (Huawei Cloud and Peking University)", "accessed": "2026-11-11", "fields": [ "fp16_tflops", "hbm_gb", "peak_note" ] }, { "url": "https://cset.georgetown.edu/publication/pushing-the-limits-huaweis-ai-chip-tests-u-s-export-controls/", "title": "CSET: Pushing the limits, Huawei's AI chip tests U.S. export controls", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "foundry", "process_node", "hbm_type", "hbm_gb", "mem_bw_tbs", "fp16_tflops", "peak_note", "status", "announced_year", "deployment_scale", "available_as" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-910c", "name": "Huawei Ascend 910C", "url": "https://www.hiascend.com/", "summary": "Two compute dies in one package: 752 dense FP16/BF16 TFLOPS, 128 GB of HBM at 3.2 TB/s, and 384 chips per CloudMatrix 384 supernode. Huawei has deployed more than 300 Atlas 900 A3 SuperPoDs.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Training and inference", "design_partner": "In-house (HiSilicon)", "foundry": "SMIC", "process_node": "SMIC N+2 (7 nm-class)", "hbm_type": "HBM", "hbm_gb": 128, "mem_bw_tbs": 3.2, "bf16_tflops": 752, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "752 dense FP16/BF16 TFLOPS across both dies (The Register); no FP8 support stated.", "cpu_cores": null, "tdp_w": null, "pod_chips": 384, "status": "Deployed", "announced_year": 2024, "deployment_scale": "More than 300 Atlas 900 A3 SuperPoDs deployed for over 20 customers (Huawei, September 2025).", "available_as": "Huawei Cloud CloudMatrix 384 instances; Atlas 900 A3 SuperPoD" }, "sources": [ { "url": "https://www.theregister.com/2025/07/29/huawei_rackscale_boogeyman/", "title": "The Register: Stacking up Huawei's rack-scale boogeyman against Nvidia's best", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "peak_note", "pod_chips" ] }, { "url": "https://technews.tw/2025/10/03/huawei-used-tsmc-samsung-sk-hynix-components-in-top-ai-chips/", "title": "TechNews: TechInsights teardown of Ascend 910C finds SMIC N+2", "accessed": "2026-11-11", "fields": [ "process_node", "design_partner", "foundry" ] }, { "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "title": "Huawei: Eric Xu keynote at Huawei Connect 2025", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale", "available_as" ] }, { "url": "https://www.design-reuse.com/news/16460-china-39-s-huawei-smic-39-to-ramp-production-39-of-newest-ai-chip", "title": "Reuters via Design & Reuse: Huawei, SMIC to ramp production of newest AI chip (Nov 2024)", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-950dt", "name": "Huawei Ascend 950DT", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "summary": "The training and decode variant of the Ascend 950: 144 GB of Huawei's HiZQ 2.0 HBM at 4 TB/s, 1 PFLOPS FP8, and up to 8,192 chips in one Atlas 950 SuperPoD. The SuperPoD is in testing, with volume supply from the end of 2026.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Training and inference", "design_partner": "In-house (HiSilicon)", "foundry": null, "process_node": null, "hbm_type": "HiZQ 2.0 (Huawei in-house HBM)", "hbm_gb": 144, "mem_bw_tbs": 4, "bf16_tflops": null, "fp8_tflops": 1000, "int8_tops": null, "fp4_tflops": 2000, "peak_note": "Same Ascend 950 die as the 950PR: 1 PFLOPS FP8 and 2 PFLOPS MXFP4 per chip.", "cpu_cores": null, "tdp_w": null, "pod_chips": 8192, "status": "Sampling", "announced_year": 2025, "deployment_scale": "Atlas 950 SuperPoD: up to 8,192 chips in 160 cabinets; volume supply expected end of 2026 or early 2027.", "available_as": "Huawei Atlas 950 SuperPoD" }, "sources": [ { "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "title": "Huawei: Eric Xu keynote at Huawei Connect 2025", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "hbm_type", "hbm_gb", "mem_bw_tbs", "fp8_tflops", "fp4_tflops", "peak_note", "pod_chips", "announced_year", "deployment_scale", "available_as" ] }, { "url": "https://www.trendforce.com/news/2026/10/07/news-huawei-says-ascend-market-share-has-surpassed-nvidia-in-china-backs-npo-over-cpo-for-optical-interconnects/", "title": "TrendForce: Huawei says Ascend market share tops NVIDIA in China", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-950pr", "name": "Huawei Ascend 950PR", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "summary": "Huawei's inference and recommendation chip on the new Ascend 950 die: 1 PFLOPS FP8 and 2 PFLOPS MXFP4, with Huawei's own low-cost HiBL 1.0 HBM. Shipping in limited volumes in 2026, and Huawei says it sells every unit it can make.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Inference", "design_partner": "In-house (HiSilicon)", "foundry": null, "process_node": null, "hbm_type": "HiBL 1.0 (Huawei in-house HBM)", "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": 1000, "int8_tops": null, "fp4_tflops": 2000, "peak_note": "Huawei states 1 PFLOPS in FP8, MXFP8 and HiF8, and 2 PFLOPS in MXFP4, per chip.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2025, "deployment_scale": "Available in limited volumes; Huawei says it is selling everything it can produce (October 2026).", "available_as": "Huawei computing cards and SuperPoD servers" }, "sources": [ { "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "title": "Huawei: Eric Xu keynote at Huawei Connect 2025", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "hbm_type", "fp8_tflops", "fp4_tflops", "peak_note", "announced_year", "available_as" ] }, { "url": "https://www.trendforce.com/news/2026/10/07/news-huawei-says-ascend-market-share-has-surpassed-nvidia-in-china-backs-npo-over-cpo-for-optical-interconnects/", "title": "TrendForce: Huawei says Ascend market share tops NVIDIA in China", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-960", "name": "Huawei Ascend 960", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "summary": "Huawei's 2027 chip: 2 PFLOPS FP8 and 4 PFLOPS FP4, double the Ascend 950's compute, memory capacity and bandwidth, and up to 15,488 chips in one Atlas 960 SuperPoD. Due in the fourth quarter of 2027.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Training and inference", "design_partner": "In-house (HiSilicon)", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": 2000, "int8_tops": null, "fp4_tflops": 4000, "peak_note": "Huawei states 2 PFLOPS FP8 and 4 PFLOPS FP4 per chip.", "cpu_cores": null, "tdp_w": null, "pod_chips": 15488, "status": "Announced", "announced_year": 2025, "deployment_scale": "Atlas 960 SuperPoD: up to 15,488 chips in 220 cabinets.", "available_as": "Huawei Atlas 960 SuperPoD (Q4 2027)" }, "sources": [ { "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "title": "Huawei: Eric Xu keynote at Huawei Connect 2025", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "fp8_tflops", "fp4_tflops", "peak_note", "pod_chips", "status", "announced_year", "deployment_scale", "available_as" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "huawei-ascend-970", "name": "Huawei Ascend 970", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "summary": "Huawei’s announced Ascend 970 roadmap targets training and inference, with market availability planned for the fourth quarter of 2028. Its original roadmap describes relative performance targets rather than final specifications.", "hq": "CN", "tags": [ "China" ], "fields": { "owner": "Huawei", "role": "Training and inference", "design_partner": null, "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Original September 2025 roadmap targets 2x Ascend 960 FP4 compute, 2x FP8 compute, 2x interconnect bandwidth and at least 1.5x memory bandwidth. Preliminary targets, not measured throughput; absolute FLOPS remain empty.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2025, "deployment_scale": "Market availability planned for 2028 (Huawei, September 2026); original September 2025 target was Q4 2028.", "available_as": null }, "sources": [ { "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "title": "Huawei: Eric Xu keynote, original Ascend 970 roadmap", "accessed": "2026-11-11", "fields": [ "owner", "role", "status", "announced_year", "peak_note", "deployment_scale" ] }, { "url": "https://www.huawei.com/en/news/2026/9/hc-wang-keynote", "title": "Huawei Connect 2026: Ascend 970 remains on the 2028 roadmap", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-300", "name": "Meta MTIA 300", "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "summary": "MTIA 300 is the base of Meta's chiplet roadmap, developed in close partnership with Broadcom and in production for ranking and recommendation training. Meta has deployed hundreds of thousands of MTIA chips in production.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Training", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 216, "mem_bw_tbs": 6.1, "bf16_tflops": 600, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Meta's chip-specifications image: 600 BF16 TFLOPS, 1200 TFLOPS in its shared FP8/MX8 row, per accelerator module. The shared FP8/MX8 figure is kept in the MX8 column and labelled here; Meta does not label sparsity. Module TDP 800 W.", "cpu_cores": null, "tdp_w": 800, "pod_chips": 16, "status": "Deployed", "announced_year": 2026, "deployment_scale": "Meta has deployed hundreds of thousands of MTIA chips in production (Meta, Mar 2026, all generations)", "available_as": "Internal only", "mx8_tflops": 1200, "mx4_tflops": null, "partner_basis": "Stated by Meta: developed in close partnership with Broadcom." }, "sources": [ { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "peak_note", "deployment_scale", "available_as", "bf16_tflops", "mx8_tflops", "hbm_gb", "mem_bw_tbs", "tdp_w", "pod_chips", "hbm_type", "partner_basis" ] }, { "url": "https://servethehome.com/meta-outlines-new-mtia-accelerator-roadmap-for-its-next-gen-ai-compute-mix", "title": "ServeTheHome: Meta outlines new MTIA accelerator roadmap for its next-gen AI compute mix", "accessed": "2026-11-11", "fields": [ "pod_chips", "status" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-400", "name": "Meta MTIA 400", "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "summary": "MTIA 400 is Meta's Broadcom-partnered inference chip with 9.2 TB/s of HBM bandwidth and 400% more FP8 compute than MTIA 300. Seventy-two MTIA 400s form one switched scale-up rack.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Training and inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 288, "mem_bw_tbs": 9.2, "bf16_tflops": 3000, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Meta's chip-specifications image: 3000 BF16 TFLOPS, 6000 TFLOPS in its shared FP8/MX8 row, 12000 MX4 TFLOPS, per accelerator module. The shared FP8/MX8 figure is kept in the MX8 column and labelled here; Meta does not label sparsity. Module TDP 1200 W.", "cpu_cores": null, "tdp_w": 1200, "pod_chips": 72, "status": "Announced", "announced_year": 2026, "deployment_scale": "Lab testing finished; on the path to data center deployment (Meta, Mar 2026)", "available_as": "Internal only", "mx8_tflops": 6000, "mx4_tflops": 12000, "partner_basis": "Stated by Meta: developed in close partnership with Broadcom." }, "sources": [ { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "peak_note", "pod_chips", "deployment_scale", "available_as", "bf16_tflops", "mx8_tflops", "mx4_tflops", "hbm_gb", "mem_bw_tbs", "tdp_w", "hbm_type", "partner_basis" ] }, { "url": "https://servethehome.com/meta-outlines-new-mtia-accelerator-roadmap-for-its-next-gen-ai-compute-mix", "title": "ServeTheHome: Meta outlines new MTIA accelerator roadmap for its next-gen AI compute mix", "accessed": "2026-11-11", "fields": [ "mem_bw_tbs", "pod_chips", "status" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-450", "name": "Meta MTIA 450", "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "summary": "MTIA 450 doubles MTIA 400's HBM bandwidth to 18.4 TB/s and lifts MX4 compute 75% for generative AI inference. Meta schedules it for mass deployment in early 2027.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": 288, "mem_bw_tbs": 18.4, "bf16_tflops": 3500, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Meta's chip-specifications image: 3500 BF16 TFLOPS, 7000 TFLOPS in its shared FP8/MX8 row, 21000 MX4 TFLOPS, per accelerator module. The shared FP8/MX8 figure is kept in the MX8 column and labelled here; Meta does not label sparsity. Module TDP 1400 W.", "cpu_cores": null, "tdp_w": 1400, "pod_chips": 72, "status": "Announced", "announced_year": 2026, "deployment_scale": "Scheduled for mass deployment in early 2027 (Meta)", "available_as": "Internal only", "mx8_tflops": 7000, "mx4_tflops": 21000, "partner_basis": "Stated by Meta: developed in close partnership with Broadcom." }, "sources": [ { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "peak_note", "deployment_scale", "available_as", "bf16_tflops", "mx8_tflops", "mx4_tflops", "hbm_gb", "mem_bw_tbs", "tdp_w", "pod_chips", "hbm_type", "partner_basis" ] }, { "url": "https://servethehome.com/meta-outlines-new-mtia-accelerator-roadmap-for-its-next-gen-ai-compute-mix", "title": "ServeTheHome: Meta outlines new MTIA accelerator roadmap for its next-gen AI compute mix", "accessed": "2026-11-11", "fields": [ "mem_bw_tbs", "status" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-500", "name": "Meta MTIA 500", "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "summary": "MTIA 500 is Meta's 2x2-chiplet inference flagship with 27.6 TB/s of HBM bandwidth, 4.5x MTIA 300, and up to 80% more HBM capacity than MTIA 450. Meta schedules it for mass deployment in 2027.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": "HBM", "hbm_gb": null, "mem_bw_tbs": 27.6, "bf16_tflops": 5000, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Meta's chip-specifications image: 5000 BF16 TFLOPS, 10000 TFLOPS in its shared FP8/MX8 row, 30000 MX4 TFLOPS, per accelerator module. The shared FP8/MX8 figure is kept in the MX8 column and labelled here; Meta does not label sparsity. Module TDP 1700 W. HBM capacity is a 384–512 GB roadmap range; the scalar capacity cell stays empty.", "cpu_cores": null, "tdp_w": 1700, "pod_chips": 72, "status": "Announced", "announced_year": 2026, "deployment_scale": "Scheduled for mass deployment in 2027 (Meta)", "available_as": "Internal only", "mx8_tflops": 10000, "mx4_tflops": 30000, "partner_basis": "Stated by Meta: developed in close partnership with Broadcom." }, "sources": [ { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "status", "announced_year", "peak_note", "deployment_scale", "available_as", "bf16_tflops", "mx8_tflops", "mx4_tflops", "mem_bw_tbs", "tdp_w", "pod_chips", "hbm_type", "partner_basis" ] }, { "url": "https://servethehome.com/meta-outlines-new-mtia-accelerator-roadmap-for-its-next-gen-ai-compute-mix", "title": "ServeTheHome: Meta outlines new MTIA accelerator roadmap for its next-gen AI compute mix", "accessed": "2026-11-11", "fields": [ "mem_bw_tbs", "peak_note", "status" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-v1", "name": "Meta MTIA v1", "url": "https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/", "summary": "Meta's first in-house AI accelerator, built for its recommendation workloads on TSMC 7nm, delivers 102.4 TOPS INT8 at just 25 W. Meta now calls it MTIA 100.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Inference", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC 7nm", "hbm_type": "LPDDR5", "hbm_gb": 64, "mem_bw_tbs": 0.176, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": 102.4, "fp4_tflops": null, "peak_note": "FP16 figure (51.2 TFLOPS). Off-chip memory is LPDDR5, not HBM: 64 GB at 176 GB/s per Meta's 2024 comparison table (the 2023 post says it can scale to 128 GB). 128 MB on-chip SRAM, 800 MHz.", "cpu_cores": null, "tdp_w": 25, "pod_chips": null, "status": "Deployed", "announced_year": 2023, "deployment_scale": null, "available_as": "Internal only", "fp16_tflops": 51.2 }, "sources": [ { "url": "https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/", "title": "Meta AI: MTIA v1: Meta's first-generation AI inference accelerator", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "fp16_tflops", "int8_tops", "tdp_w", "announced_year", "available_as", "peak_note" ] }, { "url": "https://ai.meta.com/blog/next-generation-meta-training-inference-accelerator-AI-MTIA/", "title": "Meta AI: Our next-generation Meta Training and Inference Accelerator", "accessed": "2026-11-11", "fields": [ "hbm_type", "hbm_gb", "mem_bw_tbs", "peak_note" ] }, { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "status" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "meta-mtia-v2", "name": "Meta MTIA v2", "url": "https://ai.meta.com/blog/next-generation-meta-training-inference-accelerator-AI-MTIA/", "summary": "Meta's second-generation MTIA: 354 TOPS INT8 on TSMC 5nm at 90 W, up to 72 accelerators per rack and 3x the performance of MTIA v1 across four Meta models. Meta went from first silicon to production models in 16 regions in under nine months.", "hq": "US", "tags": [ "US platform" ], "fields": { "owner": "Meta", "role": "Inference", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC 5nm", "hbm_type": "LPDDR5", "hbm_gb": 128, "mem_bw_tbs": 0.2048, "bf16_tflops": 177, "fp8_tflops": null, "int8_tops": 354, "fp4_tflops": null, "peak_note": "Non-sparse figures; Meta also lists sparse 708 TOPS INT8 and 354 TFLOPS FP16/BF16 (not used). Off-chip memory is LPDDR5, not HBM. 256 MB on-chip SRAM, 1.35 GHz. Meta now calls it MTIA 200.", "cpu_cores": null, "tdp_w": 90, "pod_chips": 72, "status": "Deployed", "announced_year": 2024, "deployment_scale": "Production models running in 16 regions (Meta, Apr 2024)", "available_as": "Internal only" }, "sources": [ { "url": "https://ai.meta.com/blog/next-generation-meta-training-inference-accelerator-AI-MTIA/", "title": "Meta AI: Our next-generation Meta Training and Inference Accelerator", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "hbm_type", "hbm_gb", "mem_bw_tbs", "bf16_tflops", "int8_tops", "peak_note", "tdp_w", "pod_chips", "status", "announced_year", "deployment_scale", "available_as" ] }, { "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "title": "Meta AI: MTIA: scaling AI chips for billions", "accessed": "2026-11-11", "fields": [ "peak_note" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "microsoft-cobalt-100", "name": "Microsoft Cobalt 100", "url": "https://azure.microsoft.com/en-us/blog/azure-cobalt-100-based-virtual-machines-are-now-generally-available/", "summary": "Cobalt 100 is Microsoft's first in-house Arm server CPU, a 128-core chip powering Microsoft Teams and Azure SQL. Azure Cobalt 100 VMs launched in 14 regions with up to 1.4x the CPU performance of earlier Azure Arm VMs.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Microsoft", "role": "Server CPU", "design_partner": "In-house", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Microsoft: up to 40% better performance than prior Azure Arm chips; VMs scale to 96 vCPUs.", "cpu_cores": 128, "tdp_w": null, "pod_chips": null, "status": "Deployed", "announced_year": 2023, "deployment_scale": "Generally available in 14 Azure regions (Oct 2024); powers Microsoft Teams and Azure SQL", "available_as": "Azure Dpsv6, Dplsv6 and Epsv6 VMs" }, "sources": [ { "url": "https://azure.microsoft.com/en-us/blog/microsoft-azure-delivers-purpose-built-cloud-infrastructure-in-the-era-of-ai/", "title": "Microsoft Azure Blog: Microsoft Azure delivers purpose-built cloud infrastructure in the era of AI", "accessed": "2026-11-11", "fields": [ "owner", "role", "cpu_cores", "announced_year", "peak_note", "deployment_scale" ] }, { "url": "https://azure.microsoft.com/en-us/blog/azure-cobalt-100-based-virtual-machines-are-now-generally-available/", "title": "Microsoft Azure Blog: Azure Cobalt 100-based Virtual Machines are now generally available", "accessed": "2026-11-11", "fields": [ "design_partner", "status", "deployment_scale", "available_as", "peak_note" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "microsoft-cobalt-200", "name": "Microsoft Cobalt 200", "url": "https://azure.microsoft.com/en-us/blog/new-azure-cobalt-200-vms-deliver-50-performance-improvement-fully-optimized-for-modern-agentic-ai-workloads/", "summary": "Cobalt 200 is Microsoft's second Arm server CPU: 132 Neoverse V3 cores across two chiplets on TSMC 3nm, with up to 50% better CPU performance than Cobalt 100. Azure Cobalt 200 VMs are in early access preview in eight regions.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Microsoft", "role": "Server CPU", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC N3P", "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Two 66-core chiplets on Arm Neoverse CSS V3, 12 memory channels, 3 MB L2 per core, 192 MB L3. VMs scale to 128 vCPUs.", "cpu_cores": 132, "tdp_w": null, "pod_chips": null, "status": "Preview", "announced_year": 2025, "deployment_scale": "Early access preview in 8 Azure regions since June 2026; general availability not announced (Microsoft, Jun 2026)", "available_as": "Azure Dpsv7, Dplsv7, Epsv7, Mpsv4 and Lpsv5 VMs (early access preview)" }, "sources": [ { "url": "https://azure.microsoft.com/en-us/blog/new-azure-cobalt-200-vms-deliver-50-performance-improvement-fully-optimized-for-modern-agentic-ai-workloads/", "title": "Microsoft Azure Blog: New Azure Cobalt 200 VMs deliver 50% performance improvement", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "peak_note", "status", "deployment_scale", "available_as" ] }, { "url": "https://www.servethehome.com/?p=92232", "title": "ServeTheHome: Microsoft Azure Cobalt 200 launched with 132 Arm Neoverse V3 cores", "accessed": "2026-11-11", "fields": [ "cpu_cores", "peak_note", "announced_year", "status", "foundry" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "microsoft-maia-100", "name": "Microsoft Maia 100", "url": "https://azure.microsoft.com/en-us/blog/microsoft-azure-delivers-purpose-built-cloud-infrastructure-in-the-era-of-ai/", "summary": "Maia 100 is Microsoft's first custom AI accelerator: 105 billion transistors on TSMC 5nm with 64 GB of HBM2E, built for AI workloads on Azure. Microsoft runs it at 500 W per accelerator for inference.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Microsoft", "role": "Training and inference", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC 5nm", "hbm_type": "HBM2E", "hbm_gb": 64, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Supports 9-bit and 6-bit compute; about 500 MB L1/L2 cache; 12x 400GbE network. 700 W TDP part, run at 500 W in production for inference (ServeTheHome).", "cpu_cores": null, "tdp_w": 700, "pod_chips": null, "status": "Deployed", "announced_year": 2023, "deployment_scale": null, "available_as": "Internal only (Azure services)" }, "sources": [ { "url": "https://azure.microsoft.com/en-us/blog/microsoft-azure-delivers-purpose-built-cloud-infrastructure-in-the-era-of-ai/", "title": "Microsoft Azure Blog: Microsoft Azure delivers purpose-built cloud infrastructure in the era of AI", "accessed": "2026-11-11", "fields": [ "owner", "role", "process_node", "announced_year" ] }, { "url": "https://servethehome.com/microsoft-maia-100-ai-accelerator-for-azure", "title": "ServeTheHome: Microsoft Maia 100 AI Accelerator for Azure", "accessed": "2026-11-11", "fields": [ "foundry", "process_node", "hbm_type", "hbm_gb", "tdp_w", "peak_note", "status", "available_as" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "microsoft-maia-200", "name": "Microsoft Maia 200", "url": "https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/", "summary": "Maia 200 is Microsoft's inference accelerator on TSMC 3nm, with a stated minimum of 10 PFLOPS FP4 and 5 PFLOPS FP8, plus 216 GB of HBM3E at 7 TB/s. It serves OpenAI's GPT-5.2 models and Microsoft 365 Copilot and is rolling out across Azure in the US, Europe and Australia.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Microsoft", "role": "Inference", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC 3nm", "hbm_type": "HBM3E", "hbm_gb": 216, "mem_bw_tbs": 7, "bf16_tflops": null, "fp8_tflops": 5000, "int8_tops": null, "fp4_tflops": 10000, "peak_note": "Minimums: Microsoft states 'over 10 petaFLOPS' FP4 and 'over 5 petaFLOPS' FP8 per chip, stored here as floors of 10,000 and 5,000 TFLOPS. No BF16 figure. 272 MB on-chip SRAM, 140B+ transistors, 2.8 TB/s scale-up bandwidth; collectives span clusters of up to 6,144 accelerators.", "cpu_cores": null, "tdp_w": 750, "pod_chips": 6144, "status": "Deployed", "announced_year": 2026, "deployment_scale": "Serving Microsoft production workloads including Copilot; deploying across the US, Europe and Australia (Microsoft, Oct 2026)", "available_as": "Azure: Microsoft 365 Copilot in production; Microsoft Foundry and GitHub Copilot due by end of 2026; Maia SDK in preview" }, "sources": [ { "url": "https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/", "title": "Microsoft: Maia 200: The AI accelerator built for inference", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "hbm_type", "hbm_gb", "mem_bw_tbs", "peak_note", "tdp_w", "pod_chips", "status", "announced_year", "available_as" ] }, { "url": "https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/", "title": "Microsoft: Maia 200 FP4 and FP8, stated minimums ('over 10' and 'over 5' petaFLOPS)", "accessed": "2026-11-11", "fields": [ "fp8_tflops", "fp4_tflops" ] }, { "url": "https://blogs.microsoft.com/?p=52563158", "title": "Microsoft: Microsoft to expand Azure Maia system to multi-gigawatt deployments", "accessed": "2026-11-11", "fields": [ "status", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "microsoft-maia-300", "name": "Microsoft Maia 300", "url": "https://blogs.microsoft.com/?p=52563158", "summary": "Maia 300 is Microsoft's next inference accelerator, with compute chiplets on TSMC N2P and eight HBM4 stacks delivering 18 TB/s at 950 W. Microsoft puts 96 in each rack and starts production deployments in 2027.", "hq": "US", "tags": [ "US cloud" ], "fields": { "owner": "Microsoft", "role": "Inference", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC N2P", "hbm_type": "HBM4", "hbm_gb": null, "mem_bw_tbs": 18, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "Microsoft gives no per-chip FLOPS; enhanced MXFP4 support. A 96-accelerator rack holds 27.6 TB of HBM (per-chip capacity not stated) and delivers up to 7x Maia 200 rack throughput. pod_chips is the rack size; scale-up domain not stated separately.", "cpu_cores": null, "tdp_w": 950, "pod_chips": 96, "status": "Announced", "announced_year": 2026, "deployment_scale": "Production deployments begin in 2027 as part of a multi-gigawatt Azure Maia rollout (Microsoft)", "available_as": null }, "sources": [ { "url": "https://blogs.microsoft.com/?p=52563158", "title": "Microsoft: Microsoft to expand Azure Maia system to multi-gigawatt deployments", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "hbm_type", "mem_bw_tbs", "peak_note", "tdp_w", "pod_chips", "status", "announced_year", "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "openai-jalapeno", "name": "OpenAI Jalapeño", "url": "https://openai.com/index/openai-broadcom-jalapeno-inference-chip/", "summary": "OpenAI's first custom chip, an LLM inference processor co-developed with Broadcom from first design to tape-out in nine months. Engineering samples run GPT-5.3-Codex-Spark at target frequency and power, with first deployment set for the end of 2026.", "hq": "US", "tags": [ "AI lab" ], "fields": { "owner": "OpenAI", "role": "Inference", "design_partner": "Broadcom", "foundry": null, "process_node": null, "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "No throughput figures published yet; OpenAI says detailed benchmarks come later.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Sampling", "announced_year": 2026, "deployment_scale": "Part of a 10 GW program of OpenAI-designed accelerators with Broadcom (announced October 2025); initial deployment end of 2026, ramp in 2027.", "available_as": "Internal only (serves ChatGPT and OpenAI's API)", "partner_basis": "Announced jointly by OpenAI and Broadcom (reported by CNBC)." }, "sources": [ { "url": "https://www.cnbc.com/2026/06/24/openai-and-broadcom-reveal-jalapeno-first-ai-chip-in-partnership.html", "title": "CNBC: OpenAI unveils first chip as part of Broadcom deal", "accessed": "2026-11-11", "fields": [ "owner", "role", "design_partner", "announced_year", "deployment_scale", "available_as", "partner_basis" ] }, { "url": "https://interestingengineering.com/ai-robotics/openai-jalapeno-ai-inference-chip-broadcom", "title": "Interesting Engineering: OpenAI unveils Jalapeño chip for large-scale inference", "accessed": "2026-11-11", "fields": [ "status", "peak_note" ] }, { "url": "https://www.broadcom.com/company/news/product-releases/63631", "title": "Broadcom: OpenAI and Broadcom announce strategic collaboration to deploy 10 gigawatts of OpenAI-designed AI accelerators", "accessed": "2026-11-11", "fields": [ "deployment_scale" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "tesla-ai5", "name": "Tesla AI5", "url": "https://www.tesla.com/AI", "summary": "Tesla's fifth-generation in-house AI chip for its cars and Optimus robots, taped out in April 2026. Musk puts it at up to 10x AI4; TSMC and Samsung both build it, with volume production in 2027.", "hq": "US", "tags": [ "Automaker" ], "fields": { "owner": "Tesla", "role": "Inference", "design_partner": null, "foundry": "TSMC; Samsung", "process_node": "Samsung SF2T (2 nm-class) for the first prototypes", "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": "No FLOPS figure published; Musk describes AI5 as up to 10x more powerful than AI4.", "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2024, "deployment_scale": "Taped out April 2026 with first prototypes; volume production expected in 2027. Tesla calls it one of the highest-volume AI chips planned.", "available_as": "Tesla vehicles and Optimus robots" }, "sources": [ { "url": "https://technode.com/2026/04/16/tesla-completes-ai5-chip-tape-out-to-be-manufactured-by-tsmc-and-samsung/", "title": "TechNode: Tesla completes AI5 chip tape-out, to be manufactured by TSMC and Samsung", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "deployment_scale", "available_as" ] }, { "url": "https://en.sedaily.com/finance/2026/04/15/tesla-completes-ai5-chip-design-samsung-korea-fab-produces", "title": "Seoul Economic Daily: Tesla completes AI5 design; Samsung produces prototype", "accessed": "2026-11-11", "fields": [ "process_node", "status" ] }, { "url": "https://electrek.co/2026/04/15/tesla-ai5-chip-taped-out-musk-ai6-dojo3/", "title": "Electrek: Tesla taped out AI5 chip, Musk says", "accessed": "2026-11-11", "fields": [ "peak_note" ] }, { "url": "https://www.elonmuskarchive.org/video/tesla-shareholder-meeting-2024-06-13", "title": "Tesla 2024 shareholder meeting: Musk announces HW5 renamed AI5 (transcript)", "accessed": "2026-11-11", "fields": [ "announced_year" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "tesla-ai6", "name": "Tesla AI6", "url": "https://www.tesla.com/AI", "summary": "Tesla's next in-house AI chip, to be made entirely by Samsung under a $16.5 billion foundry contract running to 2033 at Samsung's Taylor, Texas fab.", "hq": "US", "tags": [ "Automaker" ], "fields": { "owner": "Tesla", "role": "Training and inference", "design_partner": null, "foundry": "Samsung", "process_node": "Samsung SF2T (2 nm-class)", "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Announced", "announced_year": 2025, "deployment_scale": "Samsung contract worth 22.8 trillion won (about $16.5 billion) through 2033, built at Taylor, Texas.", "available_as": "Tesla vehicles, Optimus robots and data centers" }, "sources": [ { "url": "https://www.datacenterdynamics.com/en/news/samsung-electronics-signs-165bn-deal-with-tesla-to-manufacture-ai6-chips-at-taylor-texas-fab/", "title": "Data Center Dynamics: Samsung signs $16.5bn deal with Tesla to manufacture AI6 chips at Taylor fab", "accessed": "2026-11-11", "fields": [ "owner", "foundry", "status", "announced_year", "deployment_scale" ] }, { "url": "https://en.sedaily.com/finance/2026/04/15/tesla-completes-ai5-chip-design-samsung-korea-fab-produces", "title": "Seoul Economic Daily: Samsung's SF2T process targets Tesla AI6", "accessed": "2026-11-11", "fields": [ "process_node" ] }, { "url": "https://techcrunch.com/2025/08/07/tesla-shuts-down-dojo-the-ai-training-supercomputer-that-musk-said-would-be-key-to-full-self-driving/", "title": "TechCrunch: Tesla shuts down Dojo", "accessed": "2026-11-11", "fields": [ "role", "available_as" ] } ], "verifiedAt": "2026-11-11", "featured": false }, { "id": "tesla-dojo-d1", "name": "Tesla Dojo D1", "url": "https://www.tesla.com/AI", "summary": "Tesla's in-house training chip for the Dojo supercomputer: 50 billion transistors on a 645 mm² die, made by TSMC at 7 nm, in production from July 2023. Tesla shut Dojo down in August 2025 to focus on AI6.", "hq": "US", "tags": [ "Automaker" ], "fields": { "owner": "Tesla", "role": "Training", "design_partner": null, "foundry": "TSMC", "process_node": "TSMC 7 nm", "hbm_type": null, "hbm_gb": null, "mem_bw_tbs": null, "bf16_tflops": null, "fp8_tflops": null, "int8_tops": null, "fp4_tflops": null, "peak_note": null, "cpu_cores": null, "tdp_w": null, "pod_chips": null, "status": "Discontinued", "announced_year": 2021, "deployment_scale": "Tesla targeted 100 exaflops of total compute by October 2024, roughly 276,000 D1 chips; it never confirmed reaching it.", "available_as": "Internal only" }, "sources": [ { "url": "https://techcrunch.com/2024/08/03/tesla-dojo-elon-musks-big-plan-to-build-an-ai-supercomputer-explained/", "title": "TechCrunch: Tesla Dojo, Elon Musk's big plan to build an AI supercomputer, explained", "accessed": "2026-11-11", "fields": [ "owner", "role", "foundry", "process_node", "announced_year", "deployment_scale", "available_as" ] }, { "url": "https://techcrunch.com/2025/08/07/tesla-shuts-down-dojo-the-ai-training-supercomputer-that-musk-said-would-be-key-to-full-self-driving/", "title": "TechCrunch: Tesla shuts down Dojo", "accessed": "2026-11-11", "fields": [ "status" ] } ], "verifiedAt": "2026-11-11", "featured": false } ] }