Microsoft Maia 200

Maia 200 is Microsoft's inference accelerator on TSMC 3nm, with a stated minimum of 10 PFLOPS FP4 and 5 PFLOPS FP8, plus 216 GB of HBM3E at 7 TB/s. It serves OpenAI's GPT-5.2 models and Microsoft 365 Copilot and is rolling out across Azure in the US, Europe and Australia. Sources and verification dates.

Memory216 GB
Bandwidth7 TB/s
FP8 minimum5,000+ TFLOPS
FP4 minimum10,000+ TFLOPS
NodeTSMC 3nm
Owner Microsoft Status Deployed US cloud

Verified

Open the primary source Compare side by side

Every published figure

Source per value
Owner The company that specified the chip and runs it in its own cloud, data centers or products.
Microsoft 1
Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
Inference 1
Foundry The fab that manufactures the die (TSMC, Samsung, SMIC, Intel).
TSMC 1
Node Process node as the owner or foundry states it, for example 'TSMC N3' or '7 nm'.
TSMC 3nm 1
Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).
HBM3E 1
Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
216 1
Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.
7 1
FP8 TFLOPS Published peak FP8 throughput per chip in TFLOPS. The precision note records sparsity where the owner states it. Blank when the owner gives no FP8 figure.
5,000 2
FP4 TFLOPS Published FP4 throughput per chip or accelerator module in TFLOPS. MXFP4 and MX4 have separate columns; see the precision note for scope.
10,000 2
Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
Minimums: Microsoft states 'over 10 petaFLOPS' FP4 and 'over 5 petaFLOPS' FP8 per chip, stored here as floors of 10,000 and 5,000 TFLOPS. No BF16 figure. 272 MB on-chip SRAM, 140B+ transistors, 2.8 TB/s scale-up bandwidth; collectives span clusters of up to 6,144 accelerators. 1
Power W Chip or package power in watts as published (TDP, TBP or typical power; the source says which).
750 1
Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
6,144 1
Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
Deployed 1
Announced Year the owner first announced the chip publicly.
2,026 1
Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.
Serving Microsoft production workloads including Copilot; deploying across the US, Europe and Australia (Microsoft, Oct 2026) 3
How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.
Azure: Microsoft 365 Copilot in production; Microsoft Foundry and GitHub Copilot due by end of 2026; Maia SDK in preview 1

Not verified in the sources reviewed: design partner, partner basis, bf16, fp16, mxfp8, mxfp4, mx8, mx4, int8.

Sources

  1. Microsoft: Maia 200: The AI accelerator built for inference accessed 2026-11-11
  2. Microsoft: Maia 200 FP4 and FP8, stated minimums ('over 10' and 'over 5' petaFLOPS) accessed 2026-11-11
  3. Microsoft: Microsoft to expand Azure Maia system to multi-gigawatt deployments accessed 2026-11-11