Google TPU v4

Owner The company that specified the chip and runs it in its own cloud, data centers or products.

Google 1

Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.

Training and inference 1

Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.

Broadcom 5

Partner basis Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.

Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed. 5

Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).

HBM2 1

Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.

32 1

Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.

1.2 1

BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.

275 1

INT8 TOPS Peak INT8 throughput per chip in TOPS, as published. Mostly given for inference chips.

275 1

Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.

Google lists 275 TFLOPS 'bf16 or int8' per chip. Measured min/mean/max power 90/170/192 W; no TDP published. 1

Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.

4,096 1

Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.

Deployed 1

Announced Year the owner first announced the chip publicly.

2,021 2

Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.

Operational at Google since 2020; dozens of 4,096-chip pods planned for Google data centers (Google, 2021) 2

How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.

Google Cloud TPU v4 1

Not verified in the sources reviewed: foundry, node, fp16, mxfp8, mxfp4, mx8, mx4, fp8, fp4, power.

1. Google Cloud: TPU v4 accessed 2026-11-11
2. Google: Google I/O 2021: Being helpful in moments that matter accessed 2026-11-11
3. Google Cloud Blog: TPU v4 provides exaFLOPS-scale ML with industry-leading efficiency accessed 2026-11-11
4. arXiv (ISCA 2023): TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning accessed 2026-11-11
5. Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports accessed 2026-11-11