Google TPU v5e

Google's cost-optimized TPU for training and serving, with 197 TFLOPS BF16 and 393 TOPS INT8 per chip in 256-chip pods. Google rates it at up to 2.5x the inference performance per dollar of TPU v4. Sources and verification dates.

Memory16 GB
Bandwidth0.8 TB/s
BF16197 TFLOPS
Largest pod256 chips
Owner Google Status Deployed US cloud

Verified

Open the primary source Compare side by side

Every published figure

Source per value
Owner The company that specified the chip and runs it in its own cloud, data centers or products.
Google 1
Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
Training and inference 1
Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.
Broadcom 3
Partner basis Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.
Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed. 3
Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
16 1
Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.
0.8 1
BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.
197 1
INT8 TOPS Peak INT8 throughput per chip in TOPS, as published. Mostly given for inference chips.
393 1
Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
Dense per-chip peaks. Google lists HBM bandwidth as 800 GiBps. 1
Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
256 1
Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
Deployed 1
Announced Year the owner first announced the chip publicly.
2,023 2
How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.
Google Cloud TPU v5e 1

Not verified in the sources reviewed: foundry, node, memory, fp16, mxfp8, mxfp4, mx8, mx4, fp8, fp4, power, deployment scale.

Sources

  1. Google Cloud: TPU v5e accessed 2026-11-11
  2. Google Cloud Blog: Announcing Cloud TPU v5e and A3 GPUs accessed 2026-11-11
  3. Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports accessed 2026-11-11