Google TPU v5p

Owner The company that specified the chip and runs it in its own cloud, data centers or products.

Google 1

Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.

Training and inference 1

Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.

Broadcom 3

Partner basis Who says so: the owner, the partner, or press reporting with the outlet named. A reported partner is not confirmed by the owner.

Reported by Reuters, citing The Information: Google has worked exclusively with Broadcom on its TPUs. No generation named; Google has not confirmed. 3

Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.

95 1

Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.

2.765 1

BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.

459 1

FP8 TFLOPS Published peak FP8 throughput per chip in TFLOPS. The precision note records sparsity where the owner states it. Blank when the owner gives no FP8 figure.

459 1

Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.

Per-chip peaks from Google's TPU v5p docs, which list 459 TFLOPS for both BF16 and FP8. HBM: 95 GiB allocatable of 96 GiB physical. 1

Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.

8,960 1

Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.

Deployed 1

Announced Year the owner first announced the chip publicly.

2,023 2

Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.

Salesforce and Lightricks named as early customers (Google, Dec 2023) 2

How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.

Google Cloud TPU v5p 1

Not verified in the sources reviewed: foundry, node, memory, fp16, mxfp8, mxfp4, mx8, mx4, int8, fp4, power.

1. Google Cloud: TPU v5p accessed 2026-11-11
2. Google Cloud Blog: Enabling next-generation AI workloads: Announcing TPU v5p and AI Hypercomputer accessed 2026-11-11
3. Reuters (via The Star): Google preparing to partner with Taiwan's MediaTek on next AI chip, Information reports accessed 2026-11-11