Huawei Ascend 910C

Two compute dies in one package: 752 dense FP16/BF16 TFLOPS, 128 GB of HBM at 3.2 TB/s, and 384 chips per CloudMatrix 384 supernode. Huawei has deployed more than 300 Atlas 900 A3 SuperPoDs. Sources and verification dates.

Memory128 GB
Bandwidth3.2 TB/s
BF16752 TFLOPS
NodeSMIC N+2 (7 nm-class)
Largest pod384 chips
Owner Huawei Status Deployed China

Verified

Open the primary source Compare side by side

Every published figure

Source per value
Owner The company that specified the chip and runs it in its own cloud, data centers or products.
Huawei 1
Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
Training and inference 1
Design partner The ASIC house that co-designed or physically implemented the chip (Broadcom, Marvell, MediaTek, Alchip, GUC and others), as stated by the owner, the partner, a filing or named trade-press reporting. 'In-house' when the owner states it designed the chip itself, including through an acquired team such as Annapurna Labs.
In-house (HiSilicon) 2
Foundry The fab that manufactures the die (TSMC, Samsung, SMIC, Intel).
SMIC 1
Node Process node as the owner or foundry states it, for example 'TSMC N3' or '7 nm'.
SMIC N+2 (7 nm-class) 2
Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).
HBM 1
Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
128 1
Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.
3.2 1
BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.
752 1
Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
752 dense FP16/BF16 TFLOPS across both dies (The Register); no FP8 support stated. 1
Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
384 1
Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
Deployed 3
Announced Year the owner first announced the chip publicly.
2,024 4
Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.
More than 300 Atlas 900 A3 SuperPoDs deployed for over 20 customers (Huawei, September 2025). 3
How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.
Huawei Cloud CloudMatrix 384 instances; Atlas 900 A3 SuperPoD 3

Not verified in the sources reviewed: partner basis, fp16, mxfp8, mxfp4, mx8, mx4, fp8, int8, fp4, power.

Sources

  1. The Register: Stacking up Huawei's rack-scale boogeyman against Nvidia's best accessed 2026-11-11
  2. TechNews: TechInsights teardown of Ascend 910C finds SMIC N+2 accessed 2026-11-11
  3. Huawei: Eric Xu keynote at Huawei Connect 2025 accessed 2026-11-11
  4. Reuters via Design & Reuse: Huawei, SMIC to ramp production of newest AI chip (Nov 2024) accessed 2026-11-11