Meta MTIA v2
Meta's second-generation MTIA: 354 TOPS INT8 on TSMC 5nm at 90 W, up to 72 accelerators per rack and 3x the performance of MTIA v1 across four Meta models. Meta went from first silicon to production models in 16 regions in under nine months. Sources and verification dates.
Every published figure
Source per value- Owner The company that specified the chip and runs it in its own cloud, data centers or products.
- Meta 1
- Role What the owner says the chip is for: training, inference, both, or a general-purpose server CPU.
- Inference 1
- Foundry The fab that manufactures the die (TSMC, Samsung, SMIC, Intel).
- TSMC 1
- Node Process node as the owner or foundry states it, for example 'TSMC N3' or '7 nm'.
- TSMC 5nm 1
- Memory On-package memory type (HBM2e, HBM3, HBM3E, LPDDR5) or, for CPUs, the memory the socket drives (DDR5).
- LPDDR5 1
- Memory capacity GB On-package memory per chip in GB. Blank for CPUs, whose memory sits off-package.
- 128 1
- Memory bandwidth TB/s Peak memory bandwidth per chip in TB/s, as published.
- 0.205 1
- BF16 TFLOPS Published BF16 throughput per chip or accelerator module in TFLOPS. FP16 is a separate column. See the precision note for sparsity and module scope.
- 177 1
- INT8 TOPS Peak INT8 throughput per chip in TOPS, as published. Mostly given for inference chips.
- 354 1
- Precision note What the throughput figures mean: dense or sparse, which precision, per chip or per package, and any figure the owner states only in another unit.
- Non-sparse figures; Meta also lists sparse 708 TOPS INT8 and 354 TFLOPS FP16/BF16 (not used). Off-chip memory is LPDDR5, not HBM. 256 MB on-chip SRAM, 1.35 GHz. Meta now calls it MTIA 200. 1
- Power W Chip or package power in watts as published (TDP, TBP or typical power; the source says which).
- 90 1
- Largest pod chips The largest scale-up domain the owner states: chips per pod, UltraServer, supernode or rack joined by the chip-to-chip interconnect.
- 72 1
- Status Announced: public roadmap without verified deployment. Sampling: first silicon or limited internal use. Preview: customers can request early access, without a GA claim. Deployed: stated production use or general availability. Discontinued: program stopped.
- Deployed 1
- Announced Year the owner first announced the chip publicly.
- 2,024 1
- Deployment scale The largest deployment the owner or a named report states: chip counts, clusters, gigawatts or regions.
- Production models running in 16 regions (Meta, Apr 2024) 1
- How to get it How an outside buyer can use the chip: a named cloud instance or service, a product, or 'Internal only'.
- Internal only 1
Not verified in the sources reviewed: design partner, partner basis, fp16, mxfp8, mxfp4, mx8, mx4, fp8, fp4.
Sources
- Meta AI: Our next-generation Meta Training and Inference Accelerator accessed 2026-11-11
- Meta AI: MTIA: scaling AI chips for billions accessed 2026-11-11